From b974e0babeb068c9d991c28d4e1d4f33303594e0 Mon Sep 17 00:00:00 2001 From: Tim Northover Date: Fri, 17 Jul 2015 03:31:50 +0000 Subject: [PATCH] AArch64: add comment missed out from earlier patch. Helps explain some of the background behind this bit of code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242503 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/AArch64/AArch64ISelDAGToDAG.cpp | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp b/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp index cf33782365b..1a1b58bd26e 100644 --- a/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp +++ b/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp @@ -2062,6 +2062,10 @@ SDNode *AArch64DAGToDAGISel::SelectLIBM(SDNode *N) { SmallVector Ops; Ops.push_back(In); + // C11 leaves it implementation-defined whether these operations trigger an + // inexact exception. IEEE says they don't. Unfortunately, Darwin decided + // they do so we sometimes have to insert a special instruction just to set + // the right bit in FPSR. if (Subtarget->isTargetDarwin() && !TM.Options.UnsafeFPMath) { SDNode *FRINTX = CurDAG->getMachineNode(FRINTXOpc, dl, VT, MVT::Glue, In); Ops.push_back(SDValue(FRINTX, 1));