From b97aec663b1591e71c9ddee6dbb327d1b827eda5 Mon Sep 17 00:00:00 2001 From: Dale Johannesen Date: Tue, 13 Nov 2007 19:13:01 +0000 Subject: [PATCH] Add parameter to getDwarfRegNum to permit targets to use different mappings for EH and debug info; no functional change yet. Fix warning in X86CodeEmitter. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44056 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/Target/MRegisterInfo.h | 6 ++++-- lib/CodeGen/DwarfWriter.cpp | 22 +++++++++++----------- lib/Target/ARM/ARMRegisterInfo.cpp | 2 +- lib/Target/ARM/ARMRegisterInfo.h | 2 +- lib/Target/Alpha/AlphaRegisterInfo.cpp | 2 +- lib/Target/Alpha/AlphaRegisterInfo.h | 2 +- lib/Target/IA64/IA64RegisterInfo.cpp | 2 +- lib/Target/IA64/IA64RegisterInfo.h | 2 +- lib/Target/Mips/MipsRegisterInfo.cpp | 2 +- lib/Target/Mips/MipsRegisterInfo.h | 2 +- lib/Target/PowerPC/PPCRegisterInfo.cpp | 2 +- lib/Target/PowerPC/PPCRegisterInfo.h | 2 +- lib/Target/PowerPC/PPCTargetAsmInfo.cpp | 2 +- lib/Target/Sparc/SparcRegisterInfo.cpp | 2 +- lib/Target/Sparc/SparcRegisterInfo.h | 2 +- lib/Target/X86/X86CodeEmitter.cpp | 1 - lib/Target/X86/X86RegisterInfo.cpp | 2 +- lib/Target/X86/X86RegisterInfo.h | 2 +- lib/Target/X86/X86TargetAsmInfo.cpp | 3 +-- utils/TableGen/RegisterInfoEmitter.cpp | 2 +- 20 files changed, 32 insertions(+), 32 deletions(-) diff --git a/include/llvm/Target/MRegisterInfo.h b/include/llvm/Target/MRegisterInfo.h index cfe304fcd4f..bff74de8823 100644 --- a/include/llvm/Target/MRegisterInfo.h +++ b/include/llvm/Target/MRegisterInfo.h @@ -677,8 +677,10 @@ public: /// Debug information queries. /// getDwarfRegNum - Map a target register to an equivalent dwarf register - /// number. Returns -1 if there is no equivalent value. - virtual int getDwarfRegNum(unsigned RegNum) const = 0; + /// number. Returns -1 if there is no equivalent value. The second + /// parameter allows targets to use different numberings for EH info and + /// deubgging info. + virtual int getDwarfRegNum(unsigned RegNum, bool isEH) const = 0; /// getFrameRegister - This method should return the register used as a base /// for values allocated in the current stack frame. diff --git a/lib/CodeGen/DwarfWriter.cpp b/lib/CodeGen/DwarfWriter.cpp index e6ec43eed3d..2efb8002f62 100644 --- a/lib/CodeGen/DwarfWriter.cpp +++ b/lib/CodeGen/DwarfWriter.cpp @@ -968,7 +968,7 @@ public: /// EmitFrameMoves - Emit frame instructions to describe the layout of the /// frame. void EmitFrameMoves(const char *BaseLabel, unsigned BaseLabelID, - const std::vector &Moves) { + const std::vector &Moves, bool isEH) { int stackGrowth = Asm->TM.getFrameInfo()->getStackGrowthDirection() == TargetFrameInfo::StackGrowsUp ? @@ -1010,7 +1010,7 @@ public: } else { Asm->EmitInt8(DW_CFA_def_cfa); Asm->EOL("DW_CFA_def_cfa"); - Asm->EmitULEB128Bytes(RI->getDwarfRegNum(Src.getRegister())); + Asm->EmitULEB128Bytes(RI->getDwarfRegNum(Src.getRegister(), isEH)); Asm->EOL("Register"); } @@ -1026,13 +1026,13 @@ public: if (Dst.isRegister()) { Asm->EmitInt8(DW_CFA_def_cfa_register); Asm->EOL("DW_CFA_def_cfa_register"); - Asm->EmitULEB128Bytes(RI->getDwarfRegNum(Dst.getRegister())); + Asm->EmitULEB128Bytes(RI->getDwarfRegNum(Dst.getRegister(), isEH)); Asm->EOL("Register"); } else { assert(0 && "Machine move no supported yet."); } } else { - unsigned Reg = RI->getDwarfRegNum(Src.getRegister()); + unsigned Reg = RI->getDwarfRegNum(Src.getRegister(), isEH); int Offset = Dst.getOffset() / stackGrowth; if (Offset < 0) { @@ -1340,7 +1340,7 @@ private: /// provided. void AddAddress(DIE *Die, unsigned Attribute, const MachineLocation &Location) { - unsigned Reg = RI->getDwarfRegNum(Location.getRegister()); + unsigned Reg = RI->getDwarfRegNum(Location.getRegister(), false); DIEBlock *Block = new DIEBlock(); if (Location.isRegister()) { @@ -2370,13 +2370,13 @@ private: Asm->EOL("CIE Code Alignment Factor"); Asm->EmitSLEB128Bytes(stackGrowth); Asm->EOL("CIE Data Alignment Factor"); - Asm->EmitInt8(RI->getDwarfRegNum(RI->getRARegister())); + Asm->EmitInt8(RI->getDwarfRegNum(RI->getRARegister(), false)); Asm->EOL("CIE RA Column"); std::vector Moves; RI->getInitialFrameState(Moves); - EmitFrameMoves(NULL, 0, Moves); + EmitFrameMoves(NULL, 0, Moves, false); Asm->EmitAlignment(2); EmitLabel("debug_frame_common_end", 0); @@ -2409,7 +2409,7 @@ private: "func_begin", DebugFrameInfo.Number); Asm->EOL("FDE address range"); - EmitFrameMoves("func_begin", DebugFrameInfo.Number, DebugFrameInfo.Moves); + EmitFrameMoves("func_begin", DebugFrameInfo.Number, DebugFrameInfo.Moves, false); Asm->EmitAlignment(2); EmitLabel("debug_frame_end", DebugFrameInfo.Number); @@ -2817,7 +2817,7 @@ private: Asm->EOL("CIE Code Alignment Factor"); Asm->EmitSLEB128Bytes(stackGrowth); Asm->EOL("CIE Data Alignment Factor"); - Asm->EmitInt8(RI->getDwarfRegNum(RI->getRARegister())); + Asm->EmitInt8(RI->getDwarfRegNum(RI->getRARegister(), true)); Asm->EOL("CIE RA Column"); // If there is a personality, we need to indicate the functions location. @@ -2853,7 +2853,7 @@ private: // Indicate locations of general callee saved registers in frame. std::vector Moves; RI->getInitialFrameState(Moves); - EmitFrameMoves(NULL, 0, Moves); + EmitFrameMoves(NULL, 0, Moves, true); Asm->EmitAlignment(2); EmitLabel("eh_frame_common_end", Index); @@ -2915,7 +2915,7 @@ private: // Indicate locations of function specific callee saved registers in // frame. - EmitFrameMoves("eh_func_begin", EHFrameInfo.Number, EHFrameInfo.Moves); + EmitFrameMoves("eh_func_begin", EHFrameInfo.Number, EHFrameInfo.Moves, true); Asm->EmitAlignment(2); EmitLabel("eh_frame_end", EHFrameInfo.Number); diff --git a/lib/Target/ARM/ARMRegisterInfo.cpp b/lib/Target/ARM/ARMRegisterInfo.cpp index b4cd0c79dd2..b5c04bab0f3 100644 --- a/lib/Target/ARM/ARMRegisterInfo.cpp +++ b/lib/Target/ARM/ARMRegisterInfo.cpp @@ -1660,7 +1660,7 @@ unsigned ARMRegisterInfo::getEHHandlerRegister() const { return 0; } -int ARMRegisterInfo::getDwarfRegNum(unsigned RegNum) const { +int ARMRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const { assert(0 && "What is the dwarf register number"); return -1; } diff --git a/lib/Target/ARM/ARMRegisterInfo.h b/lib/Target/ARM/ARMRegisterInfo.h index 7d25fdcfc62..b1110db8f0f 100644 --- a/lib/Target/ARM/ARMRegisterInfo.h +++ b/lib/Target/ARM/ARMRegisterInfo.h @@ -118,7 +118,7 @@ public: unsigned getEHExceptionRegister() const; unsigned getEHHandlerRegister() const; - int getDwarfRegNum(unsigned RegNum) const; + int getDwarfRegNum(unsigned RegNum, bool isEH) const; }; } // end namespace llvm diff --git a/lib/Target/Alpha/AlphaRegisterInfo.cpp b/lib/Target/Alpha/AlphaRegisterInfo.cpp index 6cf9df71346..3d1747e8cfb 100644 --- a/lib/Target/Alpha/AlphaRegisterInfo.cpp +++ b/lib/Target/Alpha/AlphaRegisterInfo.cpp @@ -480,7 +480,7 @@ unsigned AlphaRegisterInfo::getEHHandlerRegister() const { return 0; } -int AlphaRegisterInfo::getDwarfRegNum(unsigned RegNum) const { +int AlphaRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const { assert(0 && "What is the dwarf register number"); return -1; } diff --git a/lib/Target/Alpha/AlphaRegisterInfo.h b/lib/Target/Alpha/AlphaRegisterInfo.h index cd7d47591da..6275cb4057e 100644 --- a/lib/Target/Alpha/AlphaRegisterInfo.h +++ b/lib/Target/Alpha/AlphaRegisterInfo.h @@ -93,7 +93,7 @@ struct AlphaRegisterInfo : public AlphaGenRegisterInfo { unsigned getEHExceptionRegister() const; unsigned getEHHandlerRegister() const; - int getDwarfRegNum(unsigned RegNum) const; + int getDwarfRegNum(unsigned RegNum, bool isEH) const; static std::string getPrettyName(unsigned reg); }; diff --git a/lib/Target/IA64/IA64RegisterInfo.cpp b/lib/Target/IA64/IA64RegisterInfo.cpp index a1c4e1ec190..af1af3110dd 100644 --- a/lib/Target/IA64/IA64RegisterInfo.cpp +++ b/lib/Target/IA64/IA64RegisterInfo.cpp @@ -451,7 +451,7 @@ unsigned IA64RegisterInfo::getEHHandlerRegister() const { return 0; } -int IA64RegisterInfo::getDwarfRegNum(unsigned RegNum) const { +int IA64RegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const { assert(0 && "What is the dwarf register number"); return -1; } diff --git a/lib/Target/IA64/IA64RegisterInfo.h b/lib/Target/IA64/IA64RegisterInfo.h index d30e28e9576..3f86a4c1743 100644 --- a/lib/Target/IA64/IA64RegisterInfo.h +++ b/lib/Target/IA64/IA64RegisterInfo.h @@ -85,7 +85,7 @@ struct IA64RegisterInfo : public IA64GenRegisterInfo { unsigned getEHExceptionRegister() const; unsigned getEHHandlerRegister() const; - int getDwarfRegNum(unsigned RegNum) const; + int getDwarfRegNum(unsigned RegNum, bool isEH) const; }; } // End llvm namespace diff --git a/lib/Target/Mips/MipsRegisterInfo.cpp b/lib/Target/Mips/MipsRegisterInfo.cpp index ed9f7e23ef1..9dc85638843 100644 --- a/lib/Target/Mips/MipsRegisterInfo.cpp +++ b/lib/Target/Mips/MipsRegisterInfo.cpp @@ -539,7 +539,7 @@ getEHHandlerRegister() const { } int MipsRegisterInfo:: -getDwarfRegNum(unsigned RegNum) const { +getDwarfRegNum(unsigned RegNum, bool isEH) const { assert(0 && "What is the dwarf register number"); return -1; } diff --git a/lib/Target/Mips/MipsRegisterInfo.h b/lib/Target/Mips/MipsRegisterInfo.h index 28f693647d6..636ffb9f431 100644 --- a/lib/Target/Mips/MipsRegisterInfo.h +++ b/lib/Target/Mips/MipsRegisterInfo.h @@ -97,7 +97,7 @@ struct MipsRegisterInfo : public MipsGenRegisterInfo { unsigned getEHExceptionRegister() const; unsigned getEHHandlerRegister() const; - int getDwarfRegNum(unsigned RegNum) const; + int getDwarfRegNum(unsigned RegNum, bool isEH) const; }; } // end namespace llvm diff --git a/lib/Target/PowerPC/PPCRegisterInfo.cpp b/lib/Target/PowerPC/PPCRegisterInfo.cpp index cac3d7956ba..950d4408fb9 100644 --- a/lib/Target/PowerPC/PPCRegisterInfo.cpp +++ b/lib/Target/PowerPC/PPCRegisterInfo.cpp @@ -1277,7 +1277,7 @@ unsigned PPCRegisterInfo::getEHHandlerRegister() const { return !Subtarget.isPPC64() ? PPC::R4 : PPC::X4; } -int PPCRegisterInfo::getDwarfRegNum(unsigned RegNum) const { +int PPCRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const { // FIXME: Most probably dwarf numbers differs for Linux and Darwin return PPCGenRegisterInfo::getDwarfRegNumFull(RegNum, 0); } diff --git a/lib/Target/PowerPC/PPCRegisterInfo.h b/lib/Target/PowerPC/PPCRegisterInfo.h index 8dd86e5269e..776d11cd073 100644 --- a/lib/Target/PowerPC/PPCRegisterInfo.h +++ b/lib/Target/PowerPC/PPCRegisterInfo.h @@ -117,7 +117,7 @@ public: unsigned getEHExceptionRegister() const; unsigned getEHHandlerRegister() const; - int getDwarfRegNum(unsigned RegNum) const; + int getDwarfRegNum(unsigned RegNum, bool isEH) const; }; } // end namespace llvm diff --git a/lib/Target/PowerPC/PPCTargetAsmInfo.cpp b/lib/Target/PowerPC/PPCTargetAsmInfo.cpp index 992b090edd5..6b43ecbba5a 100644 --- a/lib/Target/PowerPC/PPCTargetAsmInfo.cpp +++ b/lib/Target/PowerPC/PPCTargetAsmInfo.cpp @@ -58,7 +58,7 @@ DarwinTargetAsmInfo::DarwinTargetAsmInfo(const PPCTargetMachine &TM) UsedDirective = "\t.no_dead_strip\t"; WeakRefDirective = "\t.weak_reference\t"; HiddenDirective = "\t.private_extern\t"; - SupportsExceptionHandling = false; + SupportsExceptionHandling = true; NeedsIndirectEncoding = true; BSSSection = 0; diff --git a/lib/Target/Sparc/SparcRegisterInfo.cpp b/lib/Target/Sparc/SparcRegisterInfo.cpp index 54afccafc6e..f3e2ff88600 100644 --- a/lib/Target/Sparc/SparcRegisterInfo.cpp +++ b/lib/Target/Sparc/SparcRegisterInfo.cpp @@ -333,7 +333,7 @@ unsigned SparcRegisterInfo::getEHHandlerRegister() const { return 0; } -int SparcRegisterInfo::getDwarfRegNum(unsigned RegNum) const { +int SparcRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const { assert(0 && "What is the dwarf register number"); return -1; } diff --git a/lib/Target/Sparc/SparcRegisterInfo.h b/lib/Target/Sparc/SparcRegisterInfo.h index 267ce25f415..dec01e02769 100644 --- a/lib/Target/Sparc/SparcRegisterInfo.h +++ b/lib/Target/Sparc/SparcRegisterInfo.h @@ -97,7 +97,7 @@ struct SparcRegisterInfo : public SparcGenRegisterInfo { unsigned getEHExceptionRegister() const; unsigned getEHHandlerRegister() const; - int getDwarfRegNum(unsigned RegNum) const; + int getDwarfRegNum(unsigned RegNum, bool isEH) const; }; } // end namespace llvm diff --git a/lib/Target/X86/X86CodeEmitter.cpp b/lib/Target/X86/X86CodeEmitter.cpp index 8102ce61e00..cf1dda47901 100644 --- a/lib/Target/X86/X86CodeEmitter.cpp +++ b/lib/Target/X86/X86CodeEmitter.cpp @@ -384,7 +384,6 @@ static unsigned sizeOfImm(const TargetInstrDescriptor *Desc) { /// e.g. r8, xmm8, etc. bool Emitter::isX86_64ExtendedReg(const MachineOperand &MO) { if (!MO.isRegister()) return false; - unsigned RegNo = MO.getReg(); switch (MO.getReg()) { default: break; case X86::R8: case X86::R9: case X86::R10: case X86::R11: diff --git a/lib/Target/X86/X86RegisterInfo.cpp b/lib/Target/X86/X86RegisterInfo.cpp index ee754dfb4e0..71f8d0e7855 100644 --- a/lib/Target/X86/X86RegisterInfo.cpp +++ b/lib/Target/X86/X86RegisterInfo.cpp @@ -657,7 +657,7 @@ X86RegisterInfo::X86RegisterInfo(X86TargetMachine &tm, // getDwarfRegNum - This function maps LLVM register identifiers to the // Dwarf specific numbering, used in debug info and exception tables. -int X86RegisterInfo::getDwarfRegNum(unsigned RegNo) const { +int X86RegisterInfo::getDwarfRegNum(unsigned RegNo, bool isEH) const { const X86Subtarget *Subtarget = &TM.getSubtarget(); unsigned Flavour = DWARFFlavour::X86_64; if (!Subtarget->is64Bit()) { diff --git a/lib/Target/X86/X86RegisterInfo.h b/lib/Target/X86/X86RegisterInfo.h index 30902889cfb..18e8b907c3a 100644 --- a/lib/Target/X86/X86RegisterInfo.h +++ b/lib/Target/X86/X86RegisterInfo.h @@ -87,7 +87,7 @@ public: /// getDwarfRegNum - allows modification of X86GenRegisterInfo::getDwarfRegNum /// (created by TableGen) for target dependencies. - int getDwarfRegNum(unsigned RegNum) const; + int getDwarfRegNum(unsigned RegNum, bool isEH) const; /// Code Generation virtual methods... /// diff --git a/lib/Target/X86/X86TargetAsmInfo.cpp b/lib/Target/X86/X86TargetAsmInfo.cpp index 05cf2bfdaba..060e00d804d 100644 --- a/lib/Target/X86/X86TargetAsmInfo.cpp +++ b/lib/Target/X86/X86TargetAsmInfo.cpp @@ -101,8 +101,7 @@ X86TargetAsmInfo::X86TargetAsmInfo(const X86TargetMachine &TM) { DwarfMacInfoSection = ".section __DWARF,__debug_macinfo,regular,debug"; // Exceptions handling - if (!Subtarget->is64Bit()) - SupportsExceptionHandling = true; + SupportsExceptionHandling = true; AbsoluteEHSectionOffsets = false; DwarfEHFrameSection = ".section __TEXT,__eh_frame,coalesced,no_toc+strip_static_syms+live_support"; diff --git a/utils/TableGen/RegisterInfoEmitter.cpp b/utils/TableGen/RegisterInfoEmitter.cpp index e48c85d8e7f..fad0331a112 100644 --- a/utils/TableGen/RegisterInfoEmitter.cpp +++ b/utils/TableGen/RegisterInfoEmitter.cpp @@ -62,7 +62,7 @@ void RegisterInfoEmitter::runHeader(std::ostream &OS) { << "(int CallFrameSetupOpcode = -1, int CallFrameDestroyOpcode = -1);\n" << " virtual int getDwarfRegNumFull(unsigned RegNum, " << "unsigned Flavour) const;\n" - << " virtual int getDwarfRegNum(unsigned RegNum) const = 0;\n" + << " virtual int getDwarfRegNum(unsigned RegNum, bool isEH) const = 0;\n" << " unsigned getSubReg(unsigned RegNo, unsigned Index) const;\n" << "};\n\n";