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Generalize the handling of call and return arguments,
in preparation for apint support. These changes are intended to have no functional effect. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46967 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -620,14 +620,19 @@ public:
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} // end namespace llvm
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/// getCopyFromParts - Create a value that contains the
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/// specified legal parts combined into the value they represent.
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/// getCopyFromParts - Create a value that contains the specified legal parts
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/// combined into the value they represent. If the parts combine to a type
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/// larger then ValueVT then AssertOp can be used to specify whether the extra
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/// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
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/// (ISD::AssertSext). Likewise TruncExact is used for floating point types to
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/// indicate that the extra bits can be discarded without losing precision.
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static SDOperand getCopyFromParts(SelectionDAG &DAG,
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const SDOperand *Parts,
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unsigned NumParts,
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MVT::ValueType PartVT,
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MVT::ValueType ValueVT,
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ISD::NodeType AssertOp = ISD::DELETED_NODE) {
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ISD::NodeType AssertOp = ISD::DELETED_NODE,
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bool TruncExact = false) {
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if (!MVT::isVector(ValueVT) || NumParts == 1) {
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SDOperand Val = Parts[0];
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@ -675,7 +680,8 @@ static SDOperand getCopyFromParts(SelectionDAG &DAG,
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}
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if (MVT::isFloatingPoint(PartVT) && MVT::isFloatingPoint(ValueVT))
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return DAG.getNode(ISD::FP_ROUND, ValueVT, Val, DAG.getIntPtrConstant(0));
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return DAG.getNode(ISD::FP_ROUND, ValueVT, Val,
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DAG.getIntPtrConstant(TruncExact));
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if (MVT::getSizeInBits(PartVT) == MVT::getSizeInBits(ValueVT))
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return DAG.getNode(ISD::BIT_CONVERT, ValueVT, Val);
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@ -723,13 +729,15 @@ static SDOperand getCopyFromParts(SelectionDAG &DAG,
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ValueVT, &Ops[0], NumIntermediates);
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}
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/// getCopyToParts - Create a series of nodes that contain the
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/// specified value split into legal parts.
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/// getCopyToParts - Create a series of nodes that contain the specified value
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/// split into legal parts. If the parts contain more bits than Val, then, for
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/// integers, ExtendKind can be used to specify how to generate the extra bits.
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static void getCopyToParts(SelectionDAG &DAG,
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SDOperand Val,
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SDOperand *Parts,
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unsigned NumParts,
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MVT::ValueType PartVT) {
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MVT::ValueType PartVT,
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ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
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TargetLowering &TLI = DAG.getTargetLoweringInfo();
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MVT::ValueType PtrVT = TLI.getPointerTy();
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MVT::ValueType ValueVT = Val.getValueType();
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@ -763,7 +771,7 @@ static void getCopyToParts(SelectionDAG &DAG,
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if (PartVT < ValueVT)
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Val = DAG.getNode(ISD::TRUNCATE, PartVT, Val);
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else
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Val = DAG.getNode(ISD::ANY_EXTEND, PartVT, Val);
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Val = DAG.getNode(ExtendKind, PartVT, Val);
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} else if (MVT::isFloatingPoint(PartVT) &&
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MVT::isFloatingPoint(ValueVT)) {
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Val = DAG.getNode(ISD::FP_EXTEND, PartVT, Val);
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@ -919,38 +927,32 @@ void SelectionDAGLowering::visitRet(ReturnInst &I) {
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NewValues.push_back(getRoot());
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for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) {
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SDOperand RetOp = getValue(I.getOperand(i));
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// If this is an integer return value, we need to promote it ourselves to
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// the full width of a register, since getCopyToParts and Legalize will use
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// ANY_EXTEND rather than sign/zero.
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MVT::ValueType VT = RetOp.getValueType();
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// FIXME: C calling convention requires the return type to be promoted to
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// at least 32-bit. But this is not necessary for non-C calling conventions.
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if (MVT::isInteger(RetOp.getValueType()) &&
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RetOp.getValueType() < MVT::i64) {
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MVT::ValueType TmpVT;
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if (TLI.getTypeAction(MVT::i32) == TargetLowering::Promote)
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TmpVT = TLI.getTypeToTransformTo(MVT::i32);
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else
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TmpVT = MVT::i32;
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const Function *F = I.getParent()->getParent();
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ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
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if (F->paramHasAttr(0, ParamAttr::SExt))
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ExtendKind = ISD::SIGN_EXTEND;
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if (F->paramHasAttr(0, ParamAttr::ZExt))
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ExtendKind = ISD::ZERO_EXTEND;
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RetOp = DAG.getNode(ExtendKind, TmpVT, RetOp);
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NewValues.push_back(RetOp);
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if (MVT::isInteger(VT)) {
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MVT::ValueType MinVT = TLI.getRegisterType(MVT::i32);
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if (MVT::getSizeInBits(VT) < MVT::getSizeInBits(MinVT))
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VT = MinVT;
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}
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unsigned NumParts = TLI.getNumRegisters(VT);
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MVT::ValueType PartVT = TLI.getRegisterType(VT);
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SmallVector<SDOperand, 4> Parts(NumParts);
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ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
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const Function *F = I.getParent()->getParent();
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if (F->paramHasAttr(0, ParamAttr::SExt))
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ExtendKind = ISD::SIGN_EXTEND;
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else if (F->paramHasAttr(0, ParamAttr::ZExt))
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ExtendKind = ISD::ZERO_EXTEND;
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getCopyToParts(DAG, RetOp, &Parts[0], NumParts, PartVT, ExtendKind);
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for (unsigned i = 0; i < NumParts; ++i) {
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NewValues.push_back(Parts[i]);
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NewValues.push_back(DAG.getConstant(false, MVT::i32));
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} else {
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MVT::ValueType VT = RetOp.getValueType();
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unsigned NumParts = TLI.getNumRegisters(VT);
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MVT::ValueType PartVT = TLI.getRegisterType(VT);
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SmallVector<SDOperand, 4> Parts(NumParts);
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getCopyToParts(DAG, RetOp, &Parts[0], NumParts, PartVT);
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for (unsigned i = 0; i < NumParts; ++i) {
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NewValues.push_back(Parts[i]);
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NewValues.push_back(DAG.getConstant(false, MVT::i32));
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}
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}
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}
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DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other,
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@ -3953,32 +3955,16 @@ TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
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if (F.paramHasAttr(j, ParamAttr::Nest))
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Flags |= ISD::ParamFlags::Nest;
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Flags |= (OriginalAlignment << ISD::ParamFlags::OrigAlignmentOffs);
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switch (getTypeAction(VT)) {
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default: assert(0 && "Unknown type action!");
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case Legal:
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RetVals.push_back(VT);
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MVT::ValueType RegisterVT = getRegisterType(VT);
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unsigned NumRegs = getNumRegisters(VT);
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for (unsigned i = 0; i != NumRegs; ++i) {
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RetVals.push_back(RegisterVT);
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// if it isn't first piece, alignment must be 1
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if (i > 0)
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Flags = (Flags & (~ISD::ParamFlags::OrigAlignment)) |
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(1 << ISD::ParamFlags::OrigAlignmentOffs);
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Ops.push_back(DAG.getConstant(Flags, MVT::i32));
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break;
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case Promote:
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RetVals.push_back(getTypeToTransformTo(VT));
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Ops.push_back(DAG.getConstant(Flags, MVT::i32));
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break;
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case Expand: {
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// If this is an illegal type, it needs to be broken up to fit into
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// registers.
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MVT::ValueType RegisterVT = getRegisterType(VT);
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unsigned NumRegs = getNumRegisters(VT);
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for (unsigned i = 0; i != NumRegs; ++i) {
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RetVals.push_back(RegisterVT);
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// if it isn't first piece, alignment must be 1
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if (i > 0)
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Flags = (Flags & (~ISD::ParamFlags::OrigAlignment)) |
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(1 << ISD::ParamFlags::OrigAlignmentOffs);
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Ops.push_back(DAG.getConstant(Flags, MVT::i32));
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}
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break;
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}
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}
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}
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@ -3998,39 +3984,21 @@ TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
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for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
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++I, ++Idx) {
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MVT::ValueType VT = getValueType(I->getType());
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switch (getTypeAction(VT)) {
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default: assert(0 && "Unknown type action!");
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case Legal:
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Ops.push_back(SDOperand(Result, i++));
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break;
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case Promote: {
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SDOperand Op(Result, i++);
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if (MVT::isInteger(VT)) {
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if (F.paramHasAttr(Idx, ParamAttr::SExt))
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Op = DAG.getNode(ISD::AssertSext, Op.getValueType(), Op,
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DAG.getValueType(VT));
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else if (F.paramHasAttr(Idx, ParamAttr::ZExt))
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Op = DAG.getNode(ISD::AssertZext, Op.getValueType(), Op,
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DAG.getValueType(VT));
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Op = DAG.getNode(ISD::TRUNCATE, VT, Op);
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} else {
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assert(MVT::isFloatingPoint(VT) && "Not int or FP?");
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Op = DAG.getNode(ISD::FP_ROUND, VT, Op, DAG.getIntPtrConstant(1));
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}
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Ops.push_back(Op);
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break;
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}
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case Expand: {
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MVT::ValueType PartVT = getRegisterType(VT);
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unsigned NumParts = getNumRegisters(VT);
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SmallVector<SDOperand, 4> Parts(NumParts);
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for (unsigned j = 0; j != NumParts; ++j)
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Parts[j] = SDOperand(Result, i++);
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Ops.push_back(getCopyFromParts(DAG, &Parts[0], NumParts, PartVT, VT));
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break;
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}
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}
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MVT::ValueType PartVT = getRegisterType(VT);
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unsigned NumParts = getNumRegisters(VT);
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SmallVector<SDOperand, 4> Parts(NumParts);
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for (unsigned j = 0; j != NumParts; ++j)
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Parts[j] = SDOperand(Result, i++);
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ISD::NodeType AssertOp = ISD::DELETED_NODE;
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if (F.paramHasAttr(Idx, ParamAttr::SExt))
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AssertOp = ISD::AssertSext;
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else if (F.paramHasAttr(Idx, ParamAttr::ZExt))
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AssertOp = ISD::AssertZext;
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Ops.push_back(getCopyFromParts(DAG, &Parts[0], NumParts, PartVT, VT,
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AssertOp, true));
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}
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assert(i == NumArgRegs && "Argument register count mismatch!");
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return Ops;
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@ -4082,47 +4050,28 @@ TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
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if (Args[i].isNest)
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Flags |= ISD::ParamFlags::Nest;
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Flags |= OriginalAlignment << ISD::ParamFlags::OrigAlignmentOffs;
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switch (getTypeAction(VT)) {
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default: assert(0 && "Unknown type action!");
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case Legal:
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Ops.push_back(Op);
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Ops.push_back(DAG.getConstant(Flags, MVT::i32));
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break;
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case Promote:
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if (MVT::isInteger(VT)) {
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unsigned ExtOp;
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if (Args[i].isSExt)
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ExtOp = ISD::SIGN_EXTEND;
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else if (Args[i].isZExt)
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ExtOp = ISD::ZERO_EXTEND;
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else
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ExtOp = ISD::ANY_EXTEND;
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Op = DAG.getNode(ExtOp, getTypeToTransformTo(VT), Op);
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} else {
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assert(MVT::isFloatingPoint(VT) && "Not int or FP?");
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Op = DAG.getNode(ISD::FP_EXTEND, getTypeToTransformTo(VT), Op);
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}
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Ops.push_back(Op);
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Ops.push_back(DAG.getConstant(Flags, MVT::i32));
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break;
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case Expand: {
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MVT::ValueType PartVT = getRegisterType(VT);
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unsigned NumParts = getNumRegisters(VT);
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SmallVector<SDOperand, 4> Parts(NumParts);
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getCopyToParts(DAG, Op, &Parts[0], NumParts, PartVT);
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for (unsigned i = 0; i != NumParts; ++i) {
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// if it isn't first piece, alignment must be 1
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unsigned MyFlags = Flags;
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if (i != 0)
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MyFlags = (MyFlags & (~ISD::ParamFlags::OrigAlignment)) |
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(1 << ISD::ParamFlags::OrigAlignmentOffs);
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Ops.push_back(Parts[i]);
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Ops.push_back(DAG.getConstant(MyFlags, MVT::i32));
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}
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break;
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}
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MVT::ValueType PartVT = getRegisterType(VT);
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unsigned NumParts = getNumRegisters(VT);
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SmallVector<SDOperand, 4> Parts(NumParts);
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ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
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if (Args[i].isSExt)
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ExtendKind = ISD::SIGN_EXTEND;
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else if (Args[i].isZExt)
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ExtendKind = ISD::ZERO_EXTEND;
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getCopyToParts(DAG, Op, &Parts[0], NumParts, PartVT, ExtendKind);
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for (unsigned i = 0; i != NumParts; ++i) {
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// if it isn't first piece, alignment must be 1
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unsigned MyFlags = Flags;
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if (i != 0)
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MyFlags = (MyFlags & (~ISD::ParamFlags::OrigAlignment)) |
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(1 << ISD::ParamFlags::OrigAlignmentOffs);
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Ops.push_back(Parts[i]);
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Ops.push_back(DAG.getConstant(MyFlags, MVT::i32));
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}
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}
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