6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-12-13 20:32:21 +00:00
Code Issues Projects Releases Wiki Activity

Check that subregisters don't have independent values in RemoveCopyByCommutingDef().

Browse Source 
This fixes PR6941.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102970 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen 2010-05-03 22:40:32 +00:00
parent d4d01154ef
commit b98c549d13
2 changed files with 47 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

17
lib/CodeGen/SimpleRegisterCoalescing.cpp
View File

@ -259,6 +259,9 @@ bool SimpleRegisterCoalescing::HasOtherReachingDefs(LiveInterval &IntA,
for (; BI != IntB.ranges.end() && AI->end >= BI->start; ++BI) {
if (BI->valno == BValNo)
continue;
// When BValNo is null, we're looking for a dummy clobber-value for a subreg.
if (!BValNo && !BI->valno->isDefAccurate() && !BI->valno->getCopy())
continue;
if (BI->start <= AI->start && BI->end > AI->start)
return true;
if (BI->start > AI->start && BI->start < AI->end)
@ -369,6 +372,17 @@ bool SimpleRegisterCoalescing::RemoveCopyByCommutingDef(LiveInterval &IntA,
if (HasOtherReachingDefs(IntA, IntB, AValNo, BValNo))
return false;
bool BHasSubRegs = false;
if (TargetRegisterInfo::isPhysicalRegister(IntB.reg))
BHasSubRegs = *tri_->getSubRegisters(IntB.reg);
// Abort if the subregisters of IntB.reg have values that are not simply the
// clobbers from the superreg.
if (BHasSubRegs)
for (const unsigned *SR = tri_->getSubRegisters(IntB.reg); *SR; ++SR)
if (HasOtherReachingDefs(IntA, li_->getInterval(*SR), AValNo, 0))
return false;
// If some of the uses of IntA.reg is already coalesced away, return false.
// It's not possible to determine whether it's safe to perform the coalescing.
for (MachineRegisterInfo::use_nodbg_iterator UI =
@ -417,9 +431,6 @@ bool SimpleRegisterCoalescing::RemoveCopyByCommutingDef(LiveInterval &IntA,
BExtend[ALR->end] = BLR->end;
// Update uses of IntA of the specific Val# with IntB.
bool BHasSubRegs = false;
if (TargetRegisterInfo::isPhysicalRegister(IntB.reg))
BHasSubRegs = *tri_->getSubRegisters(IntB.reg);
for (MachineRegisterInfo::use_iterator UI = mri_->use_begin(IntA.reg),
UE = mri_->use_end(); UI != UE;) {
MachineOperand &UseMO = UI.getOperand();

33
test/CodeGen/X86/2010-05-03-CoalescerSubRegClobber.ll Normal file
View File

@ -0,0 +1,33 @@
; RUN: llc < %s | FileCheck %s
; PR6941
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
target triple = "x86_64-apple-darwin10.0.0"
define i32 @snd_xbytes(i32 %v, i32 %from, i32 %to) nounwind readnone ssp {
entry:
%cmp19 = icmp eq i32 %to, 0 ; <i1> [#uses=1]
br i1 %cmp19, label %while.end, label %while.cond
while.cond: ; preds = %entry, %while.cond
%y.021 = phi i32 [ %rem, %while.cond ], [ %to, %entry ] ; <i32> [#uses=3]
%x.020 = phi i32 [ %y.021, %while.cond ], [ %from, %entry ] ; <i32> [#uses=1]
%rem = urem i32 %x.020, %y.021 ; <i32> [#uses=2]
%cmp = icmp eq i32 %rem, 0 ; <i1> [#uses=1]
br i1 %cmp, label %while.end, label %while.cond
while.end: ; preds = %while.cond, %entry
%x.0.lcssa = phi i32 [ %from, %entry ], [ %y.021, %while.cond ] ; <i32> [#uses=2]
%div = udiv i32 %from, %x.0.lcssa ; <i32> [#uses=1]
%div11 = udiv i32 %to, %x.0.lcssa ; <i32> [#uses=1]
%conv = zext i32 %v to i64 ; <i64> [#uses=1]
%conv14 = zext i32 %div11 to i64 ; <i64> [#uses=1]
; Verify that we don't clobber %eax after putting the imulq result in %rax
; CHECK: imulq %r{{.}}x, %r[[RES:.]]x
; CHECK-NOT: movl {{.*}}, %e[[RES]]x
; CHECK: div
%mul = mul i64 %conv14, %conv ; <i64> [#uses=1]
%conv16 = zext i32 %div to i64 ; <i64> [#uses=1]
%div17 = udiv i64 %mul, %conv16 ; <i64> [#uses=1]
%conv18 = trunc i64 %div17 to i32 ; <i32> [#uses=1]
ret i32 %conv18
}