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fix ComputeMaskedBits handling of zext/sext/trunc to work with vectors.

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This fixes PR4905


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81174 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner
2009-09-08 00:13:52 +00:00
parent cf5128ec01
commit b9a4ddbbcd
2 changed files with 30 additions and 8 deletions
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15
lib/Analysis/ValueTracking.cpp
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@@ -232,12 +232,16 @@ void llvm::ComputeMaskedBits(Value *V, const APInt &Mask,
// FALL THROUGH and handle them the same as zext/trunc. // FALL THROUGH and handle them the same as zext/trunc.
case Instruction::ZExt: case Instruction::ZExt:
case Instruction::Trunc: { case Instruction::Trunc: {
const Type *SrcTy = I->getOperand(0)->getType();
unsigned SrcBitWidth;
// Note that we handle pointer operands here because of inttoptr/ptrtoint // Note that we handle pointer operands here because of inttoptr/ptrtoint
// which fall through here. // which fall through here.
const Type *SrcTy = I->getOperand(0)->getType(); if (isa<PointerType>(SrcTy))
unsigned SrcBitWidth = TD ? SrcBitWidth = TD->getTypeSizeInBits(SrcTy);
TD->getTypeSizeInBits(SrcTy) : else
SrcTy->getScalarSizeInBits(); SrcBitWidth = SrcTy->getScalarSizeInBits();
APInt MaskIn(Mask); APInt MaskIn(Mask);
MaskIn.zextOrTrunc(SrcBitWidth); MaskIn.zextOrTrunc(SrcBitWidth);
KnownZero.zextOrTrunc(SrcBitWidth); KnownZero.zextOrTrunc(SrcBitWidth);
@@ -265,8 +269,7 @@ void llvm::ComputeMaskedBits(Value *V, const APInt &Mask,
} }
case Instruction::SExt: { case Instruction::SExt: {
// Compute the bits in the result that are not present in the input. // Compute the bits in the result that are not present in the input.
const IntegerType *SrcTy = cast<IntegerType>(I->getOperand(0)->getType()); unsigned SrcBitWidth = I->getOperand(0)->getType()->getScalarSizeInBits();
unsigned SrcBitWidth = SrcTy->getBitWidth();
APInt MaskIn(Mask); APInt MaskIn(Mask);
MaskIn.trunc(SrcBitWidth); MaskIn.trunc(SrcBitWidth);

23
test/Transforms/InstCombine/crash.ll
View File

@@ -1,8 +1,8 @@
; RUN: llvm-as < %s | opt -instcombine | llvm-dis ; RUN: opt < %s -instcombine | llvm-dis
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128" target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
target triple = "i386-apple-darwin10.0" target triple = "i386-apple-darwin10.0"
define i32 @_Z9model8bitR5Mixeri(i8 %tmp2) ssp { define i32 @test0(i8 %tmp2) ssp {
entry: entry:
%tmp3 = zext i8 %tmp2 to i32 %tmp3 = zext i8 %tmp2 to i32
%tmp8 = lshr i32 %tmp3, 6 %tmp8 = lshr i32 %tmp3, 6
@@ -12,3 +12,22 @@ entry:
%tmp12 = xor i32 %tmp11, 0 %tmp12 = xor i32 %tmp11, 0
ret i32 %tmp12 ret i32 %tmp12
} }
; PR4905
define <2 x i64> @test1(<2 x i64> %x, <2 x i64> %y) nounwind {
entry:
%conv.i94 = bitcast <2 x i64> %y to <4 x i32> ; <<4 x i32>> [#uses=1]
%sub.i97 = sub <4 x i32> %conv.i94, undef ; <<4 x i32>> [#uses=1]
%conv3.i98 = bitcast <4 x i32> %sub.i97 to <2 x i64> ; <<2 x i64>> [#uses=2]
%conv2.i86 = bitcast <2 x i64> %conv3.i98 to <4 x i32> ; <<4 x i32>> [#uses=1]
%cmp.i87 = icmp sgt <4 x i32> undef, %conv2.i86 ; <<4 x i1>> [#uses=1]
%sext.i88 = sext <4 x i1> %cmp.i87 to <4 x i32> ; <<4 x i32>> [#uses=1]
%conv3.i89 = bitcast <4 x i32> %sext.i88 to <2 x i64> ; <<2 x i64>> [#uses=1]
%and.i = and <2 x i64> %conv3.i89, %conv3.i98 ; <<2 x i64>> [#uses=1]
%or.i = or <2 x i64> zeroinitializer, %and.i ; <<2 x i64>> [#uses=1]
%conv2.i43 = bitcast <2 x i64> %or.i to <4 x i32> ; <<4 x i32>> [#uses=1]
%sub.i = sub <4 x i32> zeroinitializer, %conv2.i43 ; <<4 x i32>> [#uses=1]
%conv3.i44 = bitcast <4 x i32> %sub.i to <2 x i64> ; <<2 x i64>> [#uses=1]
ret <2 x i64> %conv3.i44
}