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fix register corruption! (my god.) r15 is a scratch reg, using that as

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a frame pointer is a pretty doofus thing to do. use r5 instead, and
mark it callee-saved, coz that's what it is!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25526 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Duraid Madina 2006-01-23 06:08:46 +00:00
parent 7070c5f241
commit b9bcd18794
3 changed files with 13 additions and 11 deletions
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6
lib/Target/IA64/IA64.td
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@ -39,9 +39,11 @@ def IA64 : Target {
//'preserved' GRs: //'preserved' GRs:
[ [
r5 // the 'frame pointer' (base pointer) reg
// We never generate references to these regs, so we don't need to declare // We never generate references to these regs, so we don't need to declare
// that they are saved. In fact, we could just remove them entirely. // that they are saved. In fact, we could just remove them entirely.
//r4, r5, r6, r7, //r4, r6, r7,
//'special' GRs: //'special' GRs:
@ -49,7 +51,7 @@ def IA64 : Target {
// r12, // memory stack pointer (SP)- XXX NOT callee saved, we do it ourselves // r12, // memory stack pointer (SP)- XXX NOT callee saved, we do it ourselves
// rp, // return branch register (rp/b0) - we do this ourselves // rp, // return branch register (rp/b0) - we do this ourselves
// **** r13 (thread pointer) we do not touch, ever. it's not here. ****// // **** r13 (thread pointer) we do not touch, ever. it's not here. ****//
//r15, // our frame pointer (FP) //r15,
//'stacked' GRs the RSE takes care of, we don't worry about //'stacked' GRs the RSE takes care of, we don't worry about
/* We don't want PEI::calculateCallerSavedRegisters to worry about them, /* We don't want PEI::calculateCallerSavedRegisters to worry about them,

10
lib/Target/IA64/IA64RegisterInfo.cpp
View File

@ -152,7 +152,7 @@ void IA64RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const
int FrameIndex = MI.getOperand(i).getFrameIndex(); int FrameIndex = MI.getOperand(i).getFrameIndex();
// choose a base register: ( hasFP? framepointer : stack pointer ) // choose a base register: ( hasFP? framepointer : stack pointer )
unsigned BaseRegister = FP ? IA64::r15 : IA64::r12; unsigned BaseRegister = FP ? IA64::r5 : IA64::r12;
// Add the base register // Add the base register
MI.SetMachineOperandReg(i, BaseRegister); MI.SetMachineOperandReg(i, BaseRegister);
@ -276,10 +276,10 @@ void IA64RegisterInfo::emitPrologue(MachineFunction &MF) const {
// now if we need to, save the old FP and set the new // now if we need to, save the old FP and set the new
if (FP) { if (FP) {
MI = BuildMI(IA64::ST8, 2).addReg(IA64::r12).addReg(IA64::r15); MI = BuildMI(IA64::ST8, 2).addReg(IA64::r12).addReg(IA64::r5);
MBB.insert(MBBI, MI); MBB.insert(MBBI, MI);
// this must be the last instr in the prolog ? (XXX: why??) // this must be the last instr in the prolog ? (XXX: why??)
MI = BuildMI(IA64::MOV, 1, IA64::r15).addReg(IA64::r12); MI = BuildMI(IA64::MOV, 1, IA64::r5).addReg(IA64::r12);
MBB.insert(MBBI, MI); MBB.insert(MBBI, MI);
} }
@ -302,10 +302,10 @@ void IA64RegisterInfo::emitEpilogue(MachineFunction &MF,
if (FP) if (FP)
{ {
//copy the FP into the SP (discards allocas) //copy the FP into the SP (discards allocas)
MI=BuildMI(IA64::MOV, 1, IA64::r12).addReg(IA64::r15); MI=BuildMI(IA64::MOV, 1, IA64::r12).addReg(IA64::r5);
MBB.insert(MBBI, MI); MBB.insert(MBBI, MI);
//restore the FP //restore the FP
MI=BuildMI(IA64::LD8, 1, IA64::r15).addReg(IA64::r15); MI=BuildMI(IA64::LD8, 1, IA64::r5).addReg(IA64::r5);
MBB.insert(MBBI, MI); MBB.insert(MBBI, MI);
} }

8
lib/Target/IA64/IA64RegisterInfo.td
View File

@ -226,7 +226,7 @@ def B6 : GR<0, "b6">;
// //
// these are the scratch (+stacked) general registers // these are the scratch (+stacked) general registers
// FIXME/XXX we also reserve a frame pointer (r15) // FIXME/XXX we also reserve a frame pointer (r5)
// FIXME/XXX we also reserve r2 for spilling/filling predicates // FIXME/XXX we also reserve r2 for spilling/filling predicates
// in IA64RegisterInfo.cpp // in IA64RegisterInfo.cpp
// FIXME/XXX we also reserve r22 for calculating addresses // FIXME/XXX we also reserve r22 for calculating addresses
@ -239,7 +239,7 @@ def GR : RegisterClass<"IA64", [i64], 64,
// registers to be the first ones allocated // registers to be the first ones allocated
out7, out6, out5, out4, out3, out2, out1, out0, out7, out6, out5, out4, out3, out2, out1, out0,
r3, r8, r9, r10, r11, r14, r3, r8, r9, r10, r11, r14, r15,
r16, r17, r18, r19, r20, r21, r23, r16, r17, r18, r19, r20, r21, r23,
r24, r25, r26, r27, r28, r29, r30, r31, r24, r25, r26, r27, r28, r29, r30, r31,
r32, r33, r34, r35, r36, r37, r38, r39, r32, r33, r34, r35, r36, r37, r38, r39,
@ -254,7 +254,7 @@ def GR : RegisterClass<"IA64", [i64], 64,
r104, r105, r106, r107, r108, r109, r110, r111, r104, r105, r106, r107, r108, r109, r110, r111,
r112, r113, r114, r115, r116, r117, r118, r119, r112, r113, r114, r115, r116, r117, r118, r119,
r120, r121, r122, r123, r124, r125, r126, r127, r120, r121, r122, r123, r124, r125, r126, r127,
r0, r1, r2, r12, r13, r15, r22, rp]> // the last 16 are special (look down) r0, r1, r2, r5, r12, r13, r22, rp]> // the last 16 are special (look down)
{ {
let MethodProtos = [{ let MethodProtos = [{
iterator allocation_order_begin(MachineFunction &MF) const; iterator allocation_order_begin(MachineFunction &MF) const;
@ -269,7 +269,7 @@ def GR : RegisterClass<"IA64", [i64], 64,
GRClass::iterator GRClass::iterator
GRClass::allocation_order_end(MachineFunction &MF) const { GRClass::allocation_order_end(MachineFunction &MF) const {
int numReservedRegs=8; // the 8 special registers r0,r1,r2,r12,r13 etc int numReservedRegs=8; // the 8 special registers r0,r1,r2,r5,r12,r13 etc
// we also can't allocate registers for use as locals if they're // we also can't allocate registers for use as locals if they're
// already required as 'out' registers // already required as 'out' registers