mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-22 10:29:35 +00:00
[SystemZ] Allow integer AND involving high words
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191762 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Richard Sandiford
parent
1ff62e182e
commit
b9dcca8265
@ -127,6 +127,9 @@ void SystemZAsmPrinter::EmitInstruction(const MachineInstr *MI) {
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LOWER_HIGH(IIHL);
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LOWER_HIGH(IIHH);
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LOWER_HIGH(NIHL);
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LOWER_HIGH(NIHH);
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LOWER_HIGH(NIHF);
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LOWER_HIGH(OIHL);
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LOWER_HIGH(OIHH);
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LOWER_HIGH(OIHF);
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@ -2963,14 +2963,14 @@ EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const {
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return emitAtomicLoadBinary(MI, MBB, SystemZ::NILL64, 64);
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case SystemZ::ATOMIC_LOAD_NILH64:
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return emitAtomicLoadBinary(MI, MBB, SystemZ::NILH64, 64);
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case SystemZ::ATOMIC_LOAD_NIHL:
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return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHL, 64);
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case SystemZ::ATOMIC_LOAD_NIHH:
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return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHH, 64);
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case SystemZ::ATOMIC_LOAD_NIHL64:
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return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHL64, 64);
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case SystemZ::ATOMIC_LOAD_NIHH64:
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return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHH64, 64);
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case SystemZ::ATOMIC_LOAD_NILF64:
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return emitAtomicLoadBinary(MI, MBB, SystemZ::NILF64, 64);
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case SystemZ::ATOMIC_LOAD_NIHF:
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return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHF, 64);
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case SystemZ::ATOMIC_LOAD_NIHF64:
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return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHF64, 64);
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case SystemZ::ATOMIC_LOADW_OR:
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return emitAtomicLoadBinary(MI, MBB, SystemZ::OR, 0);
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@ -3032,14 +3032,14 @@ EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const {
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return emitAtomicLoadBinary(MI, MBB, SystemZ::NILL64, 64, true);
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case SystemZ::ATOMIC_LOAD_NILH64i:
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return emitAtomicLoadBinary(MI, MBB, SystemZ::NILH64, 64, true);
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case SystemZ::ATOMIC_LOAD_NIHLi:
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return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHL, 64, true);
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case SystemZ::ATOMIC_LOAD_NIHHi:
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return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHH, 64, true);
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case SystemZ::ATOMIC_LOAD_NIHL64i:
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return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHL64, 64, true);
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case SystemZ::ATOMIC_LOAD_NIHH64i:
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return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHH64, 64, true);
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case SystemZ::ATOMIC_LOAD_NILF64i:
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return emitAtomicLoadBinary(MI, MBB, SystemZ::NILF64, 64, true);
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case SystemZ::ATOMIC_LOAD_NIHFi:
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return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHF, 64, true);
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case SystemZ::ATOMIC_LOAD_NIHF64i:
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return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHF64, 64, true);
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case SystemZ::ATOMIC_LOADW_MIN:
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return emitAtomicLoadMinMax(MI, MBB, SystemZ::CR,
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@ -1397,6 +1397,16 @@ class StoreRXYPseudo<SDPatternOperator operator, RegisterOperand cls,
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let AccessBytes = bytes;
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}
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// Like RotateSelectRIEf, but expanded after RA depending on the choice
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// of registers.
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class RotateSelectRIEfPseudo<RegisterOperand cls1, RegisterOperand cls2>
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: Pseudo<(outs cls1:$R1),
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(ins cls1:$R1src, cls2:$R2, uimm8:$I3, uimm8:$I4, uimm8zx6:$I5),
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[]> {
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let Constraints = "$R1 = $R1src";
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let DisableEncoding = "$R1src";
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}
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// Implements "$dst = $cc & (8 >> CC) ? $src1 : $src2", where CC is
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// the value of the PSW's 2-bit condition code field.
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class SelectWrapper<RegisterOperand cls>
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@ -616,15 +616,15 @@ namespace {
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static LogicOp interpretAndImmediate(unsigned Opcode) {
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switch (Opcode) {
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case SystemZ::NILL: return LogicOp(32, 0, 16);
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case SystemZ::NILH: return LogicOp(32, 16, 16);
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case SystemZ::NILMux: return LogicOp(32, 0, 16);
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case SystemZ::NIHMux: return LogicOp(32, 16, 16);
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case SystemZ::NILL64: return LogicOp(64, 0, 16);
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case SystemZ::NILH64: return LogicOp(64, 16, 16);
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case SystemZ::NIHL: return LogicOp(64, 32, 16);
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case SystemZ::NIHH: return LogicOp(64, 48, 16);
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case SystemZ::NILF: return LogicOp(32, 0, 32);
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case SystemZ::NIHL64: return LogicOp(64, 32, 16);
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case SystemZ::NIHH64: return LogicOp(64, 48, 16);
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case SystemZ::NIFMux: return LogicOp(32, 0, 32);
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case SystemZ::NILF64: return LogicOp(64, 0, 32);
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case SystemZ::NIHF: return LogicOp(64, 32, 32);
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case SystemZ::NIHF64: return LogicOp(64, 32, 32);
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default: return LogicOp();
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}
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}
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@ -678,34 +678,27 @@ SystemZInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
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// Try to convert an AND into an RISBG-type instruction.
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if (LogicOp And = interpretAndImmediate(Opcode)) {
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unsigned NewOpcode;
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if (And.RegSize == 64)
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NewOpcode = SystemZ::RISBG;
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else if (TM.getSubtargetImpl()->hasHighWord())
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NewOpcode = SystemZ::RISBLL;
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else
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// We can't use RISBG for 32-bit operations because it clobbers the
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// high word of the destination too.
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NewOpcode = 0;
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if (NewOpcode) {
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uint64_t Imm = MI->getOperand(2).getImm() << And.ImmLSB;
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// AND IMMEDIATE leaves the other bits of the register unchanged.
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Imm |= allOnes(And.RegSize) & ~(allOnes(And.ImmSize) << And.ImmLSB);
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unsigned Start, End;
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if (isRxSBGMask(Imm, And.RegSize, Start, End)) {
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if (NewOpcode == SystemZ::RISBLL) {
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Start &= 31;
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End &= 31;
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}
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MachineOperand &Dest = MI->getOperand(0);
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MachineOperand &Src = MI->getOperand(1);
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MachineInstrBuilder MIB =
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BuildMI(*MBB, MI, MI->getDebugLoc(), get(NewOpcode))
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.addOperand(Dest).addReg(0)
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.addReg(Src.getReg(), getKillRegState(Src.isKill()), Src.getSubReg())
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.addImm(Start).addImm(End + 128).addImm(0);
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return finishConvertToThreeAddress(MI, MIB, LV);
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uint64_t Imm = MI->getOperand(2).getImm() << And.ImmLSB;
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// AND IMMEDIATE leaves the other bits of the register unchanged.
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Imm |= allOnes(And.RegSize) & ~(allOnes(And.ImmSize) << And.ImmLSB);
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unsigned Start, End;
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if (isRxSBGMask(Imm, And.RegSize, Start, End)) {
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unsigned NewOpcode;
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if (And.RegSize == 64)
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NewOpcode = SystemZ::RISBG;
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else {
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NewOpcode = SystemZ::RISBMux;
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Start &= 31;
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End &= 31;
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}
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MachineOperand &Dest = MI->getOperand(0);
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MachineOperand &Src = MI->getOperand(1);
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MachineInstrBuilder MIB =
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BuildMI(*MBB, MI, MI->getDebugLoc(), get(NewOpcode))
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.addOperand(Dest).addReg(0)
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.addReg(Src.getReg(), getKillRegState(Src.isKill()), Src.getSubReg())
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.addImm(Start).addImm(End + 128).addImm(0);
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return finishConvertToThreeAddress(MI, MIB, LV);
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}
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}
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return 0;
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@ -889,6 +882,18 @@ SystemZInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
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expandRIPseudo(MI, SystemZ::IILH, SystemZ::IIHH, false);
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return true;
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case SystemZ::NIFMux:
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expandRIPseudo(MI, SystemZ::NILF, SystemZ::NIHF, false);
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return true;
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case SystemZ::NILMux:
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expandRIPseudo(MI, SystemZ::NILL, SystemZ::NIHL, false);
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return true;
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case SystemZ::NIHMux:
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expandRIPseudo(MI, SystemZ::NILH, SystemZ::NIHH, false);
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return true;
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case SystemZ::OIFMux:
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expandRIPseudo(MI, SystemZ::OILF, SystemZ::OIHF, false);
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return true;
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@ -905,6 +910,18 @@ SystemZInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
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expandRIPseudo(MI, SystemZ::XILF, SystemZ::XIHF, false);
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return true;
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case SystemZ::RISBMux: {
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bool DestIsHigh = isHighReg(MI->getOperand(0).getReg());
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bool SrcIsHigh = isHighReg(MI->getOperand(2).getReg());
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if (SrcIsHigh == DestIsHigh)
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MI->setDesc(get(DestIsHigh ? SystemZ::RISBHH : SystemZ::RISBLL));
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else {
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MI->setDesc(get(DestIsHigh ? SystemZ::RISBHL : SystemZ::RISBLH));
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MI->getOperand(5).setImm(MI->getOperand(5).getImm() ^ 32);
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}
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return true;
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}
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case SystemZ::ADJDYNALLOC:
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splitAdjDynAlloc(MI);
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return true;
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@ -797,20 +797,33 @@ let Defs = [CC] in {
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let isConvertibleToThreeAddress = 1 in {
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// ANDs of a 16-bit immediate, leaving other bits unaffected.
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// The CC result only reflects the 16-bit field, not the full register.
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//
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// NIxMux expands to NI[LH]x, depending on the choice of register.
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def NILMux : BinaryRIPseudo<and, GRX32, imm32ll16c>,
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Requires<[FeatureHighWord]>;
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def NIHMux : BinaryRIPseudo<and, GRX32, imm32lh16c>,
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Requires<[FeatureHighWord]>;
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def NILL : BinaryRI<"nill", 0xA57, and, GR32, imm32ll16c>;
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def NILH : BinaryRI<"nilh", 0xA56, and, GR32, imm32lh16c>;
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def NIHL : BinaryRI<"nihl", 0xA55, and, GRH32, imm32ll16c>;
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def NIHH : BinaryRI<"nihh", 0xA54, and, GRH32, imm32lh16c>;
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def NILL64 : BinaryAliasRI<and, GR64, imm64ll16c>;
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def NILH64 : BinaryAliasRI<and, GR64, imm64lh16c>;
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def NIHL : BinaryRI<"nihl", 0xA55, and, GR64, imm64hl16c>;
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def NIHH : BinaryRI<"nihh", 0xA54, and, GR64, imm64hh16c>;
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def NIHL64 : BinaryAliasRI<and, GR64, imm64hl16c>;
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def NIHH64 : BinaryAliasRI<and, GR64, imm64hh16c>;
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// ANDs of a 32-bit immediate, leaving other bits unaffected.
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// The CC result only reflects the 32-bit field, which means we can
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// use it as a zero indicator for i32 operations but not otherwise.
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let CCValues = 0xC, CompareZeroCCMask = 0x8 in
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let CCValues = 0xC, CompareZeroCCMask = 0x8 in {
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// Expands to NILF or NIHF, depending on the choice of register.
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def NIFMux : BinaryRIPseudo<and, GRX32, uimm32>,
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Requires<[FeatureHighWord]>;
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def NILF : BinaryRIL<"nilf", 0xC0B, and, GR32, uimm32>;
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def NIHF : BinaryRIL<"nihf", 0xC0A, and, GRH32, uimm32>;
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}
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def NILF64 : BinaryAliasRIL<and, GR64, imm64lf32c>;
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def NIHF : BinaryRIL<"nihf", 0xC0A, and, GR64, imm64hf32c>;
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def NIHF64 : BinaryAliasRIL<and, GR64, imm64hf32c>;
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}
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// ANDs of memory.
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@ -1014,14 +1027,15 @@ let Defs = [CC] in {
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// Forms of RISBG that only affect one word of the destination register.
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// They do not set CC.
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def RISBLL : RotateSelectAliasRIEf<GR32, GR32>, Requires<[FeatureHighWord]>;
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def RISBLH : RotateSelectAliasRIEf<GR32, GRH32>, Requires<[FeatureHighWord]>;
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def RISBHL : RotateSelectAliasRIEf<GRH32, GR32>, Requires<[FeatureHighWord]>;
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def RISBHH : RotateSelectAliasRIEf<GRH32, GRH32>, Requires<[FeatureHighWord]>;
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def RISBLG : RotateSelectRIEf<"risblg", 0xEC51, GR32, GR64>,
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Requires<[FeatureHighWord]>;
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def RISBHG : RotateSelectRIEf<"risbhg", 0xEC5D, GRH32, GR64>,
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Requires<[FeatureHighWord]>;
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def RISBMux : RotateSelectRIEfPseudo<GRX32, GRX32>, Requires<[FeatureHighWord]>;
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def RISBLL : RotateSelectAliasRIEf<GR32, GR32>, Requires<[FeatureHighWord]>;
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def RISBLH : RotateSelectAliasRIEf<GR32, GRH32>, Requires<[FeatureHighWord]>;
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def RISBHL : RotateSelectAliasRIEf<GRH32, GR32>, Requires<[FeatureHighWord]>;
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def RISBHH : RotateSelectAliasRIEf<GRH32, GRH32>, Requires<[FeatureHighWord]>;
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def RISBLG : RotateSelectRIEf<"risblg", 0xEC51, GR32, GR64>,
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Requires<[FeatureHighWord]>;
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def RISBHG : RotateSelectRIEf<"risbhg", 0xEC5D, GRH32, GR64>,
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Requires<[FeatureHighWord]>;
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// Rotate second operand left and perform a logical operation with selected
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// bits of the first operand. The CC result only describes the selected bits,
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@ -1166,10 +1180,10 @@ def ATOMIC_LOAD_NILF : AtomicLoadBinaryImm32<atomic_load_and_32, uimm32>;
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def ATOMIC_LOAD_NGR : AtomicLoadBinaryReg64<atomic_load_and_64>;
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def ATOMIC_LOAD_NILL64 : AtomicLoadBinaryImm64<atomic_load_and_64, imm64ll16c>;
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def ATOMIC_LOAD_NILH64 : AtomicLoadBinaryImm64<atomic_load_and_64, imm64lh16c>;
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def ATOMIC_LOAD_NIHL : AtomicLoadBinaryImm64<atomic_load_and_64, imm64hl16c>;
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def ATOMIC_LOAD_NIHH : AtomicLoadBinaryImm64<atomic_load_and_64, imm64hh16c>;
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def ATOMIC_LOAD_NIHL64 : AtomicLoadBinaryImm64<atomic_load_and_64, imm64hl16c>;
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def ATOMIC_LOAD_NIHH64 : AtomicLoadBinaryImm64<atomic_load_and_64, imm64hh16c>;
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def ATOMIC_LOAD_NILF64 : AtomicLoadBinaryImm64<atomic_load_and_64, imm64lf32c>;
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def ATOMIC_LOAD_NIHF : AtomicLoadBinaryImm64<atomic_load_and_64, imm64hf32c>;
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def ATOMIC_LOAD_NIHF64 : AtomicLoadBinaryImm64<atomic_load_and_64, imm64hf32c>;
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def ATOMIC_LOADW_OR : AtomicLoadWBinaryReg<z_atomic_loadw_or>;
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def ATOMIC_LOADW_OILH : AtomicLoadWBinaryImm<z_atomic_loadw_or, imm32lh16>;
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@ -1207,13 +1221,13 @@ def ATOMIC_LOAD_NILL64i : AtomicLoadBinaryImm64<atomic_load_nand_64,
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imm64ll16c>;
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def ATOMIC_LOAD_NILH64i : AtomicLoadBinaryImm64<atomic_load_nand_64,
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imm64lh16c>;
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def ATOMIC_LOAD_NIHLi : AtomicLoadBinaryImm64<atomic_load_nand_64,
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def ATOMIC_LOAD_NIHL64i : AtomicLoadBinaryImm64<atomic_load_nand_64,
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imm64hl16c>;
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def ATOMIC_LOAD_NIHHi : AtomicLoadBinaryImm64<atomic_load_nand_64,
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def ATOMIC_LOAD_NIHH64i : AtomicLoadBinaryImm64<atomic_load_nand_64,
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imm64hh16c>;
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def ATOMIC_LOAD_NILF64i : AtomicLoadBinaryImm64<atomic_load_nand_64,
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imm64lf32c>;
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def ATOMIC_LOAD_NIHFi : AtomicLoadBinaryImm64<atomic_load_nand_64,
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def ATOMIC_LOAD_NIHF64i : AtomicLoadBinaryImm64<atomic_load_nand_64,
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imm64hf32c>;
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def ATOMIC_LOADW_MIN : AtomicLoadWBinaryReg<z_atomic_loadw_min>;
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@ -437,3 +437,66 @@ define void @f20() {
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call void asm sideeffect "stepd $0", "r"(i32 %xor3)
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ret void
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}
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; Test two-operand immediate AND involving high registers.
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define void @f21() {
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; CHECK-LABEL: f21:
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; CHECK: stepa [[REG:%r[0-5]]]
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; CHECK: nihh [[REG]], 4096
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; CHECK: stepb [[REG]]
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; CHECK: nihl [[REG]], 57536
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; CHECK: stepc [[REG]]
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; CHECK: nihf [[REG]], 12345678
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; CHECK: stepd [[REG]]
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; CHECK: br %r14
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%res1 = call i32 asm "stepa $0", "=h"()
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%and1 = and i32 %res1, 268500991
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%res2 = call i32 asm "stepb $0, $1", "=h,h"(i32 %and1)
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%and2 = and i32 %res2, -8000
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%res3 = call i32 asm "stepc $0, $1", "=h,h"(i32 %and2)
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%and3 = and i32 %res3, 12345678
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call void asm sideeffect "stepd $0", "h"(i32 %and3)
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ret void
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}
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; Test two-operand immediate AND involving low registers.
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define void @f22() {
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; CHECK-LABEL: f22:
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; CHECK: stepa [[REG:%r[0-5]]]
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; CHECK: nilh [[REG]], 4096
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; CHECK: stepb [[REG]]
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; CHECK: nill [[REG]], 57536
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; CHECK: stepc [[REG]]
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; CHECK: nilf [[REG]], 12345678
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; CHECK: stepd [[REG]]
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; CHECK: br %r14
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%res1 = call i32 asm "stepa $0", "=r"()
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%and1 = and i32 %res1, 268500991
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%res2 = call i32 asm "stepb $0, $1", "=r,r"(i32 %and1)
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%and2 = and i32 %res2, -8000
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%res3 = call i32 asm "stepc $0, $1", "=r,r"(i32 %and2)
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%and3 = and i32 %res3, 12345678
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call void asm sideeffect "stepd $0", "r"(i32 %and3)
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ret void
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}
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; Test three-operand immediate AND involving mixtures of low and high registers.
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define i32 @f23(i32 %old) {
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; CHECK-LABEL: f23:
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; CHECK-DAG: risblg [[REG1:%r[0-5]]], %r2, 28, 158, 0
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; CHECK-DAG: risbhg [[REG2:%r[0-5]]], %r2, 24, 158, 32
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; CHECK: stepa %r2, [[REG1]], [[REG2]]
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; CHECK-DAG: risbhg [[REG3:%r[0-5]]], [[REG2]], 25, 159, 0
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; CHECK-DAG: risblg %r2, [[REG2]], 24, 152, 32
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; CHECK: stepb [[REG2]], [[REG3]], %r2
|
||||
; CHECK: br %r14
|
||||
%and1 = and i32 %old, 14
|
||||
%and2 = and i32 %old, 254
|
||||
%res1 = call i32 asm "stepa $1, $2, $3",
|
||||
"=h,r,r,0"(i32 %old, i32 %and1, i32 %and2)
|
||||
%and3 = and i32 %res1, 127
|
||||
%and4 = and i32 %res1, 128
|
||||
%res2 = call i32 asm "stepb $1, $2, $3",
|
||||
"=r,h,h,0"(i32 %res1, i32 %and3, i32 %and4)
|
||||
ret i32 %res2
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user