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https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-17 21:29:20 +00:00
Some splat and shuffle support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26940 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -278,6 +278,7 @@ X86TargetLowering::X86TargetLowering(TargetMachine &TM)
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setOperationAction(ISD::MUL, MVT::v4f32, Legal);
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setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
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setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Expand);
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setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
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}
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if (TM.getSubtarget<X86Subtarget>().hasSSE2()) {
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@ -299,6 +300,7 @@ X86TargetLowering::X86TargetLowering(TargetMachine &TM)
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setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Expand);
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setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
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setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
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setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
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}
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computeRegisterProperties();
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@ -1366,6 +1368,66 @@ static bool DarwinGVRequiresExtraLoad(GlobalValue *GV) {
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(GV->isExternal() && !GV->hasNotBeenReadFromBytecode()));
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}
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/// isPSHUFDMask - Return true if the specified VECTOR_SHUFFLE operand
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/// specifies a shuffle of elements that is suitable for input to PSHUFD.
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bool X86::isPSHUFDMask(SDNode *N) {
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assert(N->getOpcode() == ISD::BUILD_VECTOR);
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if (N->getNumOperands() != 4)
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return false;
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// This is a splat operation if each element of the permute is the same, and
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// if the value doesn't reference the second vector.
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SDOperand Elt = N->getOperand(0);
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assert(isa<ConstantSDNode>(Elt) && "Invalid VECTOR_SHUFFLE mask!");
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for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i) {
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assert(isa<ConstantSDNode>(N->getOperand(i)) &&
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"Invalid VECTOR_SHUFFLE mask!");
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if (cast<ConstantSDNode>(N->getOperand(i))->getValue() >= 4) return false;
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}
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return true;
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}
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/// isSplatMask - Return true if the specified VECTOR_SHUFFLE operand specifies
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/// a splat of a single element.
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bool X86::isSplatMask(SDNode *N) {
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assert(N->getOpcode() == ISD::BUILD_VECTOR);
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// We can only splat 64-bit, and 32-bit quantities.
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if (N->getNumOperands() != 4 && N->getNumOperands() != 2)
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return false;
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// This is a splat operation if each element of the permute is the same, and
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// if the value doesn't reference the second vector.
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SDOperand Elt = N->getOperand(0);
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assert(isa<ConstantSDNode>(Elt) && "Invalid VECTOR_SHUFFLE mask!");
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for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i) {
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assert(isa<ConstantSDNode>(N->getOperand(i)) &&
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"Invalid VECTOR_SHUFFLE mask!");
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if (N->getOperand(i) != Elt) return false;
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}
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// Make sure it is a splat of the first vector operand.
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return cast<ConstantSDNode>(Elt)->getValue() < N->getNumOperands();
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}
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/// getShuffleImmediate - Return the appropriate immediate to shuffle
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/// the specified isShuffleMask VECTOR_SHUFFLE mask.
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unsigned X86::getShuffleImmediate(SDNode *N) {
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unsigned NumOperands = N->getNumOperands();
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unsigned Shift = (NumOperands == 4) ? 2 : 1;
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unsigned Mask = 0;
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unsigned i = NumOperands - 1;
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do {
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Mask |= cast<ConstantSDNode>(N->getOperand(i))->getValue();
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Mask <<= Shift;
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--i;
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} while (i != 0);
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return Mask;
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}
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/// LowerOperation - Provide custom lowering hooks for some operations.
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///
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SDOperand X86TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
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@ -2141,6 +2203,28 @@ SDOperand X86TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
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SDOperand AnyExt = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, Op.getOperand(0));
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return DAG.getNode(X86ISD::SCALAR_TO_VECTOR, Op.getValueType(), AnyExt);
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}
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case ISD::VECTOR_SHUFFLE: {
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SDOperand V1 = Op.getOperand(0);
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SDOperand V2 = Op.getOperand(1);
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SDOperand PermMask = Op.getOperand(2);
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MVT::ValueType VT = Op.getValueType();
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if (V2.getOpcode() == ISD::UNDEF) {
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// Handle splat cases.
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if (X86::isSplatMask(PermMask.Val)) {
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if (VT == MVT::v2f64 || VT == MVT::v2i64)
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// Use unpcklpd
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return DAG.getNode(X86ISD::UNPCKLP, VT, V1, V1);
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// Leave the VECTOR_SHUFFLE alone. It matches SHUFP*.
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break;
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} else if (VT == MVT::v4f32 && X86::isPSHUFDMask(PermMask.Val))
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// Leave the VECTOR_SHUFFLE alone. It matches PSHUFD.
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break;
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}
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// TODO.
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assert(0);
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}
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}
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}
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@ -2175,6 +2259,7 @@ const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
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case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
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case X86ISD::Wrapper: return "X86ISD::Wrapper";
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case X86ISD::SCALAR_TO_VECTOR: return "X86ISD::SCALAR_TO_VECTOR";
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case X86ISD::UNPCKLP: return "X86ISD::UNPCKLP";
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}
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}
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@ -149,6 +149,9 @@ namespace llvm {
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/// SCALAR_TO_VECTOR - X86 version of SCALAR_TO_VECTOR. The destination base
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/// type does not have to match the operand type.
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SCALAR_TO_VECTOR,
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/// UNPCKLP - X86 unpack and interleave low instructions.
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UNPCKLP,
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};
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// X86 specific condition code. These correspond to X86_*_COND in
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@ -174,6 +177,21 @@ namespace llvm {
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};
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}
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/// Define some predicates that are used for node matching.
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namespace X86 {
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/// isPSHUFDMask - Return true if the specified VECTOR_SHUFFLE operand
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/// specifies a shuffle of elements that is suitable for input to PSHUFD.
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bool isPSHUFDMask(SDNode *N);
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/// isSplatMask - Return true if the specified VECTOR_SHUFFLE operand
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/// specifies a splat of a single element.
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bool isSplatMask(SDNode *N);
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/// getShuffleImmediate - Return the appropriate immediate to shuffle
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/// the specified isShuffleMask VECTOR_SHUFFLE mask.
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unsigned getShuffleImmediate(SDNode *N);
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}
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//===----------------------------------------------------------------------===//
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// X86TargetLowering - X86 Implementation of the TargetLowering interface
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class X86TargetLowering : public TargetLowering {
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@ -17,14 +17,19 @@
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// SSE specific DAG Nodes.
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//===----------------------------------------------------------------------===//
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def X86loadp : SDNode<"X86ISD::LOAD_PACK", SDTLoad,
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[SDNPHasChain]>;
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def X86fand : SDNode<"X86ISD::FAND", SDTFPBinOp,
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[SDNPCommutative, SDNPAssociative]>;
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def X86fxor : SDNode<"X86ISD::FXOR", SDTFPBinOp,
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[SDNPCommutative, SDNPAssociative]>;
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def X86s2vec : SDNode<"X86ISD::SCALAR_TO_VECTOR",
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SDTypeProfile<1, 1, []>, []>;
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def SDTX86Unpcklp : SDTypeProfile<1, 2,
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[SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>]>;
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def X86loadp : SDNode<"X86ISD::LOAD_PACK", SDTLoad,
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[SDNPHasChain]>;
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def X86fand : SDNode<"X86ISD::FAND", SDTFPBinOp,
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[SDNPCommutative, SDNPAssociative]>;
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def X86fxor : SDNode<"X86ISD::FXOR", SDTFPBinOp,
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[SDNPCommutative, SDNPAssociative]>;
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def X86s2vec : SDNode<"X86ISD::SCALAR_TO_VECTOR",
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SDTypeProfile<1, 1, []>, []>;
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def X86unpcklp : SDNode<"X86ISD::UNPCKLP",
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SDTX86Unpcklp, []>;
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//===----------------------------------------------------------------------===//
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// SSE pattern fragments
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@ -36,6 +41,20 @@ def X86loadpf64 : PatFrag<(ops node:$ptr), (f64 (X86loadp node:$ptr))>;
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def loadv4f32 : PatFrag<(ops node:$ptr), (v4f32 (load node:$ptr))>;
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def loadv2f64 : PatFrag<(ops node:$ptr), (v2f64 (load node:$ptr))>;
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// SHUFFLE_get_imm xform function: convert vector_shuffle mask to PSHUF*,
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// SHUF* etc. imm.
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def SHUFFLE_get_imm : SDNodeXForm<build_vector, [{
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return getI8Imm(X86::getShuffleImmediate(N));
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}]>;
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def SHUFFLE_splat_mask : PatLeaf<(build_vector), [{
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return X86::isSplatMask(N);
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}], SHUFFLE_get_imm>;
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def PSHUFD_shuffle_mask : PatLeaf<(build_vector), [{
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return X86::isPSHUFDMask(N);
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}], SHUFFLE_get_imm>;
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//===----------------------------------------------------------------------===//
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// SSE scalar FP Instructions
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//===----------------------------------------------------------------------===//
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@ -652,6 +671,21 @@ def CMPPDrm : PDI<0xC2, MRMSrcMem,
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}
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// Shuffle and unpack instructions
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def PSHUFWrr : PSI<0x70, AddRegFrm,
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(ops VR64:$dst, VR64:$src1, i8imm:$src2),
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"pshufw {$src2, $src1, $dst|$dst, $src1, $src2}", []>;
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def PSHUFWrm : PSI<0x70, MRMSrcMem,
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(ops VR64:$dst, i64mem:$src1, i8imm:$src2),
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"pshufw {$src2, $src1, $dst|$dst, $src1, $src2}", []>;
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def PSHUFDrr : PDI<0x70, AddRegFrm,
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(ops VR128:$dst, VR128:$src1, i8imm:$src2),
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"pshufd {$src2, $src1, $dst|$dst, $src1, $src2}",
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[(set VR128:$dst, (vector_shuffle (v4f32 VR128:$src1), (undef),
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PSHUFD_shuffle_mask:$src2))]>;
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def PSHUFDrm : PDI<0x70, MRMSrcMem,
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(ops VR128:$dst, i128mem:$src1, i8imm:$src2),
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"pshufd {$src2, $src1, $dst|$dst, $src1, $src2}", []>;
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def SHUFPSrr : PSI<0xC6, MRMSrcReg,
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(ops VR128:$dst, VR128:$src1, VR128:$src2, i8imm:$src3),
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"shufps {$src3, $src2, $dst|$dst, $src2, $src3}", []>;
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@ -755,3 +789,15 @@ def : Pat<(v8i16 (X86s2vec R32:$src)), (MOVD128rr R32:$src)>,
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def : Pat<(v16i8 (X86s2vec R32:$src)), (MOVD128rr R32:$src)>,
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Requires<[HasSSE2]>;
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// Splat v4f32 / v4i32
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def : Pat<(vector_shuffle (v4f32 VR128:$src), (undef), SHUFFLE_splat_mask:$sm),
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(v4f32 (SHUFPSrr VR128:$src, VR128:$src, SHUFFLE_splat_mask:$sm))>;
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def : Pat<(vector_shuffle (v4i32 VR128:$src), (undef), SHUFFLE_splat_mask:$sm),
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(v4i32 (SHUFPSrr VR128:$src, VR128:$src, SHUFFLE_splat_mask:$sm))>;
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// Splat v2f64 / v2i64
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def : Pat<(X86unpcklp (v2f64 VR128:$src1), VR128:$src2),
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(v2f64 (UNPCKLPDrr VR128:$src1, VR128:$src2))>;
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def : Pat<(X86unpcklp (v2i64 VR128:$src1), VR128:$src2),
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(v2i64 (UNPCKLPDrr VR128:$src1, VR128:$src2))>;
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