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R600/SI: implement indirect adressing for SI
Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177277 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Christian Konig
parent
2d7f19e1e9
commit
b9e8678025
@ -58,6 +58,11 @@ SITargetLowering::SITargetLowering(TargetMachine &TM) :
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computeRegisterProperties();
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setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i32, Expand);
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setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8f32, Expand);
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setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i32, Expand);
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setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16f32, Expand);
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setOperationAction(ISD::ADD, MVT::i64, Legal);
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setOperationAction(ISD::ADD, MVT::i32, Legal);
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@ -1149,6 +1149,31 @@ def SI_KILL : InstSI <
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} // end mayLoad = 1, mayStore = 1, hasSideEffects = 1
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// Uses = [EXEC], Defs = [EXEC]
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let Uses = [EXEC], Defs = [EXEC,VCC,M0] in {
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def SI_INDIRECT_SRC : InstSI <
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(outs VReg_32:$dst, SReg_64:$temp),
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(ins unknown:$src, VSrc_32:$idx, i32imm:$off),
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"SI_INDIRECT_SRC $dst, $temp, $src, $idx, $off",
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[]
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>;
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class SI_INDIRECT_DST<RegisterClass rc> : InstSI <
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(outs rc:$dst, SReg_64:$temp),
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(ins unknown:$src, VSrc_32:$idx, i32imm:$off, VReg_32:$val),
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"SI_INDIRECT_DST $dst, $temp, $src, $idx, $off, $val",
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[]
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> {
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let Constraints = "$src = $dst";
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}
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def SI_INDIRECT_DST_V2 : SI_INDIRECT_DST<VReg_64>;
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def SI_INDIRECT_DST_V4 : SI_INDIRECT_DST<VReg_128>;
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def SI_INDIRECT_DST_V8 : SI_INDIRECT_DST<VReg_256>;
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def SI_INDIRECT_DST_V16 : SI_INDIRECT_DST<VReg_512>;
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} // Uses = [EXEC,VCC,M0], Defs = [EXEC,VCC,M0]
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} // end IsCodeGenOnly, isPseudo
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def : Pat<
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@ -1521,4 +1546,48 @@ defm : SMRD_Pattern <S_LOAD_DWORD_IMM, S_LOAD_DWORD_SGPR, i32>;
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defm : SMRD_Pattern <S_LOAD_DWORDX4_IMM, S_LOAD_DWORDX4_SGPR, v16i8>;
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defm : SMRD_Pattern <S_LOAD_DWORDX8_IMM, S_LOAD_DWORDX8_SGPR, v32i8>;
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/********** ====================== **********/
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/********** Indirect adressing **********/
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/********** ====================== **********/
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multiclass SI_INDIRECT_Pattern <RegisterClass rc, ValueType vt,
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SI_INDIRECT_DST IndDst> {
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// 1. Extract with offset
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def : Pat<
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(vector_extract (vt rc:$vec),
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(i64 (zext (i32 (add VReg_32:$idx, imm:$off))))
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),
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(f32 (SI_INDIRECT_SRC (IMPLICIT_DEF), rc:$vec, VReg_32:$idx, imm:$off))
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>;
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// 2. Extract without offset
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def : Pat<
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(vector_extract (vt rc:$vec),
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(i64 (zext (i32 VReg_32:$idx)))
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),
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(f32 (SI_INDIRECT_SRC (IMPLICIT_DEF), rc:$vec, VReg_32:$idx, 0))
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>;
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// 3. Insert with offset
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def : Pat<
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(vector_insert (vt rc:$vec), (f32 VReg_32:$val),
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(i64 (zext (i32 (add VReg_32:$idx, imm:$off))))
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),
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(vt (IndDst (IMPLICIT_DEF), rc:$vec, VReg_32:$idx, imm:$off, VReg_32:$val))
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>;
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// 4. Insert without offset
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def : Pat<
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(vector_insert (vt rc:$vec), (f32 VReg_32:$val),
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(i64 (zext (i32 VReg_32:$idx)))
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),
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(vt (IndDst (IMPLICIT_DEF), rc:$vec, VReg_32:$idx, 0, VReg_32:$val))
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>;
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}
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defm : SI_INDIRECT_Pattern <VReg_64, v2f32, SI_INDIRECT_DST_V2>;
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defm : SI_INDIRECT_Pattern <VReg_128, v4f32, SI_INDIRECT_DST_V4>;
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defm : SI_INDIRECT_Pattern <VReg_256, v8f32, SI_INDIRECT_DST_V8>;
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defm : SI_INDIRECT_Pattern <VReg_512, v16f32, SI_INDIRECT_DST_V16>;
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} // End isSI predicate
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@ -66,6 +66,7 @@ private:
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static const unsigned SkipThreshold = 12;
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static char ID;
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const TargetRegisterInfo *TRI;
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const TargetInstrInfo *TII;
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bool shouldSkip(MachineBasicBlock *From, MachineBasicBlock *To);
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@ -84,9 +85,14 @@ private:
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void Kill(MachineInstr &MI);
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void Branch(MachineInstr &MI);
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void LoadM0(MachineInstr &MI, MachineInstr *MovRel);
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void IndirectSrc(MachineInstr &MI);
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void IndirectDst(MachineInstr &MI);
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public:
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SILowerControlFlowPass(TargetMachine &tm) :
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MachineFunctionPass(ID), TII(tm.getInstrInfo()) { }
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MachineFunctionPass(ID), TRI(tm.getRegisterInfo()),
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TII(tm.getInstrInfo()) { }
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virtual bool runOnMachineFunction(MachineFunction &MF);
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@ -302,6 +308,104 @@ void SILowerControlFlowPass::Kill(MachineInstr &MI) {
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MI.eraseFromParent();
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}
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void SILowerControlFlowPass::LoadM0(MachineInstr &MI, MachineInstr *MovRel) {
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MachineBasicBlock &MBB = *MI.getParent();
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DebugLoc DL = MI.getDebugLoc();
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MachineBasicBlock::iterator I = MI;
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unsigned Save = MI.getOperand(1).getReg();
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unsigned Idx = MI.getOperand(3).getReg();
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if (AMDGPU::SReg_32RegClass.contains(Idx)) {
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BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_MOV_B32), AMDGPU::M0)
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.addReg(Idx);
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MBB.insert(I, MovRel);
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MI.eraseFromParent();
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return;
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}
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assert(AMDGPU::SReg_64RegClass.contains(Save));
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assert(AMDGPU::VReg_32RegClass.contains(Idx));
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// Save the EXEC mask
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BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_MOV_B64), Save)
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.addReg(AMDGPU::EXEC);
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// Read the next variant into VCC (lower 32 bits) <- also loop target
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BuildMI(MBB, &MI, DL, TII->get(AMDGPU::V_READFIRSTLANE_B32_e32), AMDGPU::VCC)
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.addReg(Idx);
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// Move index from VCC into M0
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BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_MOV_B32), AMDGPU::M0)
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.addReg(AMDGPU::VCC);
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// Compare the just read M0 value to all possible Idx values
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BuildMI(MBB, &MI, DL, TII->get(AMDGPU::V_CMP_EQ_U32_e32), AMDGPU::VCC)
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.addReg(AMDGPU::M0)
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.addReg(Idx);
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// Update EXEC, save the original EXEC value to VCC
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BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_AND_SAVEEXEC_B64), AMDGPU::VCC)
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.addReg(AMDGPU::VCC);
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// Do the actual move
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MBB.insert(I, MovRel);
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// Update EXEC, switch all done bits to 0 and all todo bits to 1
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BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_XOR_B64), AMDGPU::EXEC)
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.addReg(AMDGPU::EXEC)
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.addReg(AMDGPU::VCC);
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// Loop back to V_READFIRSTLANE_B32 if there are still variants to cover
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BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_CBRANCH_EXECNZ))
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.addImm(-7)
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.addReg(AMDGPU::EXEC);
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// Restore EXEC
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BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_MOV_B64), AMDGPU::EXEC)
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.addReg(Save);
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MI.eraseFromParent();
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}
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void SILowerControlFlowPass::IndirectSrc(MachineInstr &MI) {
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MachineBasicBlock &MBB = *MI.getParent();
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DebugLoc DL = MI.getDebugLoc();
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unsigned Dst = MI.getOperand(0).getReg();
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unsigned Vec = MI.getOperand(2).getReg();
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unsigned Off = MI.getOperand(4).getImm();
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MachineInstr *MovRel =
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BuildMI(*MBB.getParent(), DL, TII->get(AMDGPU::V_MOVRELS_B32_e32), Dst)
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.addReg(TRI->getSubReg(Vec, AMDGPU::sub0) + Off)
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.addReg(AMDGPU::M0, RegState::Implicit)
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.addReg(Vec, RegState::Implicit);
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LoadM0(MI, MovRel);
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}
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void SILowerControlFlowPass::IndirectDst(MachineInstr &MI) {
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MachineBasicBlock &MBB = *MI.getParent();
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DebugLoc DL = MI.getDebugLoc();
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unsigned Dst = MI.getOperand(0).getReg();
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unsigned Off = MI.getOperand(4).getImm();
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unsigned Val = MI.getOperand(5).getReg();
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MachineInstr *MovRel =
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BuildMI(*MBB.getParent(), DL, TII->get(AMDGPU::V_MOVRELD_B32_e32))
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.addReg(TRI->getSubReg(Dst, AMDGPU::sub0) + Off, RegState::Define)
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.addReg(Val)
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.addReg(AMDGPU::M0, RegState::Implicit)
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.addReg(Dst, RegState::Implicit);
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LoadM0(MI, MovRel);
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}
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bool SILowerControlFlowPass::runOnMachineFunction(MachineFunction &MF) {
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bool HaveKill = false;
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@ -363,6 +467,17 @@ bool SILowerControlFlowPass::runOnMachineFunction(MachineFunction &MF) {
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case AMDGPU::S_BRANCH:
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Branch(MI);
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break;
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case AMDGPU::SI_INDIRECT_SRC:
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IndirectSrc(MI);
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break;
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case AMDGPU::SI_INDIRECT_DST_V2:
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case AMDGPU::SI_INDIRECT_DST_V4:
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case AMDGPU::SI_INDIRECT_DST_V8:
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case AMDGPU::SI_INDIRECT_DST_V16:
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IndirectDst(MI);
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break;
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}
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}
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}
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