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[PowerPC] [Constant Hoisting] Enable constant hoisting on PPC
Implements the various TTI functions to enable constant hoisting on PPC. The only significant test-suite change is this: MultiSource/Benchmarks/VersaBench/bmm/bmm - 20% speedup (which essentially reverses the slowdown from r206120). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206141 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -18,11 +18,15 @@
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#include "PPC.h"
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#include "PPCTargetMachine.h"
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#include "llvm/Analysis/TargetTransformInfo.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Target/CostTable.h"
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#include "llvm/Target/TargetLowering.h"
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using namespace llvm;
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static cl::opt<bool> DisablePPCConstHoist("disable-ppc-constant-hoisting",
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cl::desc("disable constant hoisting on PPC"), cl::init(false), cl::Hidden);
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// Declare the pass initialization routine locally as target-specific passes
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// don't havve a target-wide initialization entry point, and so we rely on the
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// pass constructor initialization.
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@ -67,6 +71,13 @@ public:
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/// \name Scalar TTI Implementations
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/// @{
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unsigned getIntImmCost(const APInt &Imm, Type *Ty) const override;
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unsigned getIntImmCost(unsigned Opcode, unsigned Idx, const APInt &Imm,
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Type *Ty) const override;
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unsigned getIntImmCost(Intrinsic::ID IID, unsigned Idx, const APInt &Imm,
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Type *Ty) const override;
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virtual PopcntSupportKind
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getPopcntSupport(unsigned TyWidth) const override;
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virtual void getUnrollingPreferences(
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@ -123,6 +134,142 @@ PPCTTI::PopcntSupportKind PPCTTI::getPopcntSupport(unsigned TyWidth) const {
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return PSK_Software;
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}
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unsigned PPCTTI::getIntImmCost(const APInt &Imm, Type *Ty) const {
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if (DisablePPCConstHoist)
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return TargetTransformInfo::getIntImmCost(Imm, Ty);
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assert(Ty->isIntegerTy());
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unsigned BitSize = Ty->getPrimitiveSizeInBits();
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if (BitSize == 0)
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return ~0U;
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if (Imm == 0)
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return TCC_Free;
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if (Imm.getBitWidth() <= 64) {
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if (isInt<16>(Imm.getSExtValue()))
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return TCC_Basic;
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if (isInt<32>(Imm.getSExtValue())) {
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// A constant that can be materialized using lis.
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if ((Imm.getZExtValue() & 0xFFFF) == 0)
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return TCC_Basic;
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return 2 * TCC_Basic;
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}
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}
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return 4 * TCC_Basic;
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}
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unsigned PPCTTI::getIntImmCost(Intrinsic::ID IID, unsigned Idx,
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const APInt &Imm, Type *Ty) const {
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if (DisablePPCConstHoist)
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return TargetTransformInfo::getIntImmCost(IID, Idx, Imm, Ty);
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assert(Ty->isIntegerTy());
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unsigned BitSize = Ty->getPrimitiveSizeInBits();
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if (BitSize == 0)
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return ~0U;
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switch (IID) {
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default: return TCC_Free;
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case Intrinsic::sadd_with_overflow:
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case Intrinsic::uadd_with_overflow:
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case Intrinsic::ssub_with_overflow:
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case Intrinsic::usub_with_overflow:
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if ((Idx == 1) && Imm.getBitWidth() <= 64 && isInt<16>(Imm.getSExtValue()))
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return TCC_Free;
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break;
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}
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return PPCTTI::getIntImmCost(Imm, Ty);
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}
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unsigned PPCTTI::getIntImmCost(unsigned Opcode, unsigned Idx, const APInt &Imm,
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Type *Ty) const {
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if (DisablePPCConstHoist)
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return TargetTransformInfo::getIntImmCost(Opcode, Idx, Imm, Ty);
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assert(Ty->isIntegerTy());
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unsigned BitSize = Ty->getPrimitiveSizeInBits();
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if (BitSize == 0)
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return ~0U;
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unsigned ImmIdx = ~0U;
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bool ShiftedFree = false, RunFree = false, UnsignedFree = false,
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ZeroFree = false;
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switch (Opcode) {
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default: return TCC_Free;
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case Instruction::GetElementPtr:
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// Always hoist the base address of a GetElementPtr. This prevents the
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// creation of new constants for every base constant that gets constant
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// folded with the offset.
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if (Idx == 0)
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return 2 * TCC_Basic;
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return TCC_Free;
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case Instruction::And:
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RunFree = true; // (for the rotate-and-mask instructions)
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// Fallthrough...
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case Instruction::Add:
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case Instruction::Or:
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case Instruction::Xor:
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ShiftedFree = true;
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// Fallthrough...
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case Instruction::Sub:
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case Instruction::Mul:
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case Instruction::Shl:
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case Instruction::LShr:
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case Instruction::AShr:
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ImmIdx = 1;
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break;
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case Instruction::ICmp:
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UnsignedFree = true;
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ImmIdx = 1;
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// Fallthrough... (zero comparisons can use record-form instructions)
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case Instruction::Select:
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ZeroFree = true;
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break;
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case Instruction::PHI:
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case Instruction::Call:
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case Instruction::Ret:
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case Instruction::Load:
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case Instruction::Store:
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break;
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}
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if (ZeroFree && Imm == 0)
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return TCC_Free;
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if (Idx == ImmIdx && Imm.getBitWidth() <= 64) {
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if (isInt<16>(Imm.getSExtValue()))
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return TCC_Free;
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if (RunFree) {
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if (Imm.getBitWidth() <= 32 &&
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(isShiftedMask_32(Imm.getZExtValue()) ||
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isShiftedMask_32(~Imm.getZExtValue())))
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return TCC_Free;
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if (ST->isPPC64() &&
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(isShiftedMask_64(Imm.getZExtValue()) ||
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isShiftedMask_64(~Imm.getZExtValue())))
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return TCC_Free;
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}
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if (UnsignedFree && isUInt<16>(Imm.getZExtValue()))
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return TCC_Free;
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if (ShiftedFree && (Imm.getZExtValue() & 0xFFFF) == 0)
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return TCC_Free;
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}
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return PPCTTI::getIntImmCost(Imm, Ty);
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}
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void PPCTTI::getUnrollingPreferences(Loop *L, UnrollingPreferences &UP) const {
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if (ST->getDarwinDirective() == PPC::DIR_A2) {
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// The A2 is in-order with a deep pipeline, and concatenation unrolling
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23
test/Transforms/ConstantHoisting/PowerPC/const-base-addr.ll
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23
test/Transforms/ConstantHoisting/PowerPC/const-base-addr.ll
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@ -0,0 +1,23 @@
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; RUN: opt -S -consthoist < %s | FileCheck %s
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target datalayout = "E-m:e-i64:64-n32:64"
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target triple = "powerpc64-unknown-linux-gnu"
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%T = type { i32, i32, i32, i32 }
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; Test if even cheap base addresses are hoisted.
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define i32 @test1() nounwind {
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; CHECK-LABEL: @test1
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; CHECK: %const = bitcast i32 12345678 to i32
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; CHECK: %1 = inttoptr i32 %const to %T*
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; CHECK: %addr1 = getelementptr %T* %1, i32 0, i32 1
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%addr1 = getelementptr %T* inttoptr (i32 12345678 to %T*), i32 0, i32 1
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%tmp1 = load i32* %addr1
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%addr2 = getelementptr %T* inttoptr (i32 12345678 to %T*), i32 0, i32 2
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%tmp2 = load i32* %addr2
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%addr3 = getelementptr %T* inttoptr (i32 12345678 to %T*), i32 0, i32 3
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%tmp3 = load i32* %addr3
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%tmp4 = add i32 %tmp1, %tmp2
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%tmp5 = add i32 %tmp3, %tmp4
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ret i32 %tmp5
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}
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4
test/Transforms/ConstantHoisting/PowerPC/lit.local.cfg
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4
test/Transforms/ConstantHoisting/PowerPC/lit.local.cfg
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@ -0,0 +1,4 @@
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targets = set(config.root.targets_to_build.split())
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if not 'PowerPC' in targets:
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config.unsupported = True
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test/Transforms/ConstantHoisting/PowerPC/masks.ll
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66
test/Transforms/ConstantHoisting/PowerPC/masks.ll
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@ -0,0 +1,66 @@
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; RUN: opt -S -consthoist < %s | FileCheck %s
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target datalayout = "E-m:e-i64:64-n32:64"
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target triple = "powerpc64-unknown-linux-gnu"
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; Here the masks are all contiguous, and should not be hoisted.
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define i32 @test1() nounwind {
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entry:
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; CHECK-LABEL: @test1
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; CHECK-NOT: bitcast i32 65535 to i32
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; CHECK: and i32 undef, 65535
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%conv121 = and i32 undef, 65535
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br i1 undef, label %if.then152, label %if.end167
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if.then152:
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; CHECK: and i32 undef, 65535
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%conv153 = and i32 undef, 65535
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br i1 undef, label %if.end167, label %end2
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if.end167:
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; CHECK: and i32 {{.*}}, 32768
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%shl161 = shl nuw nsw i32 %conv121, 15
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%0 = load i8* undef, align 1
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%conv169 = zext i8 %0 to i32
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%shl170 = shl nuw nsw i32 %conv169, 7
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%shl161.masked = and i32 %shl161, 32768
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%conv174 = or i32 %shl170, %shl161.masked
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%cmp178 = icmp ugt i32 %conv174, 32767
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br i1 %cmp178, label %end1, label %end2
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end1:
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unreachable
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end2:
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unreachable
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}
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; Here the masks are not contiguous, and should be hoisted.
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define i32 @test2() nounwind {
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entry:
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; CHECK-LABEL: @test2
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; CHECK: bitcast i32 65531 to i32
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%conv121 = and i32 undef, 65531
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br i1 undef, label %if.then152, label %if.end167
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if.then152:
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%conv153 = and i32 undef, 65531
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br i1 undef, label %if.end167, label %end2
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if.end167:
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; CHECK: add i32 {{.*}}, -32758
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%shl161 = shl nuw nsw i32 %conv121, 15
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%0 = load i8* undef, align 1
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%conv169 = zext i8 %0 to i32
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%shl170 = shl nuw nsw i32 %conv169, 7
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%shl161.masked = and i32 %shl161, 32773
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%conv174 = or i32 %shl170, %shl161.masked
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%cmp178 = icmp ugt i32 %conv174, 32767
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br i1 %cmp178, label %end1, label %end2
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end1:
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unreachable
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end2:
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unreachable
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}
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