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MachineInstrBuilderize ARM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170795 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -464,8 +464,9 @@ PredicateInstruction(MachineInstr *MI,
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unsigned Opc = MI->getOpcode();
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unsigned Opc = MI->getOpcode();
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if (isUncondBranchOpcode(Opc)) {
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if (isUncondBranchOpcode(Opc)) {
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MI->setDesc(get(getMatchingCondBranchOpcode(Opc)));
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MI->setDesc(get(getMatchingCondBranchOpcode(Opc)));
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MI->addOperand(MachineOperand::CreateImm(Pred[0].getImm()));
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MachineInstrBuilder(*MI->getParent()->getParent(), MI)
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MI->addOperand(MachineOperand::CreateReg(Pred[1].getReg(), false));
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.addImm(Pred[0].getImm())
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.addReg(Pred[1].getReg());
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return true;
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return true;
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}
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}
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@ -1717,7 +1718,7 @@ MachineInstr *ARMBaseInstrInfo::optimizeSelect(MachineInstr *MI,
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// same register as operand 0.
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// same register as operand 0.
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MachineOperand FalseReg = MI->getOperand(Invert ? 2 : 1);
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MachineOperand FalseReg = MI->getOperand(Invert ? 2 : 1);
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FalseReg.setImplicit();
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FalseReg.setImplicit();
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NewMI->addOperand(FalseReg);
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NewMI.addOperand(FalseReg);
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NewMI->tieOperands(0, NewMI->getNumOperands() - 1);
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NewMI->tieOperands(0, NewMI->getNumOperands() - 1);
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// The caller will erase MI, but not DefMI.
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// The caller will erase MI, but not DefMI.
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