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Rename TargetLowering::getNumElements and friends to
TargetLowering::getNumRegisters and similar, to avoid confusion with the actual number of elements for vector types. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37687 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -347,12 +347,12 @@ public:
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return VT == MVT::iPTR ? PointerTy : VT;
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}
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/// getNumElements - Return the number of registers that this ValueType will
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/// getNumRegisters - Return the number of registers that this ValueType will
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/// eventually require. This is one for any types promoted to live in larger
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/// registers, but may be more than one for types (like i64) that are split
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/// into pieces.
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unsigned getNumElements(MVT::ValueType VT) const {
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return NumElementsForVT[VT];
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unsigned getNumRegisters(MVT::ValueType VT) const {
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return NumRegistersForVT[VT];
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}
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/// hasTargetDAGCombine - If true, the target has custom DAG combine
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@ -1035,7 +1035,7 @@ private:
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/// RegClassForVT - This indicates the default register class to use for
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/// each ValueType the target supports natively.
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TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE];
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unsigned char NumElementsForVT[MVT::LAST_VALUETYPE];
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unsigned char NumRegistersForVT[MVT::LAST_VALUETYPE];
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/// TransformToType - For any value types we are promoting or expanding, this
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/// contains the value type that we are changing to. For Expanded types, this
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@ -290,19 +290,19 @@ FunctionLoweringInfo::FunctionLoweringInfo(TargetLowering &tli,
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if (PN->use_empty()) continue;
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MVT::ValueType VT = TLI.getValueType(PN->getType());
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unsigned NumElements;
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unsigned NumRegisters;
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if (VT != MVT::Vector)
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NumElements = TLI.getNumElements(VT);
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NumRegisters = TLI.getNumRegisters(VT);
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else {
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MVT::ValueType VT1,VT2;
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NumElements =
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NumRegisters =
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TLI.getVectorTypeBreakdown(cast<VectorType>(PN->getType()),
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VT1, VT2);
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}
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unsigned PHIReg = ValueMap[PN];
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assert(PHIReg && "PHI node does not have an assigned virtual register!");
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const TargetInstrInfo *TII = TLI.getTargetMachine().getInstrInfo();
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for (unsigned i = 0; i != NumElements; ++i)
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for (unsigned i = 0; i != NumRegisters; ++i)
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BuildMI(MBB, TII->get(TargetInstrInfo::PHI), PHIReg+i);
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}
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}
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@ -343,7 +343,7 @@ unsigned FunctionLoweringInfo::CreateRegForValue(const Value *V) {
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// The common case is that we will only create one register for this
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// value. If we have that case, create and return the virtual register.
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unsigned NV = TLI.getNumElements(VT);
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unsigned NV = TLI.getNumRegisters(VT);
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if (NV == 1) {
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// If we are promoting this value, pick the next largest supported type.
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MVT::ValueType PromotedType = TLI.getTypeToTransformTo(VT);
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@ -750,7 +750,7 @@ SDOperand SelectionDAGLowering::getValue(const Value *V) {
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// Source must be expanded. This input value is actually coming from the
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// register pair InReg and InReg+1.
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MVT::ValueType DestVT = TLI.getTypeToExpandTo(VT);
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unsigned NumVals = TLI.getNumElements(VT);
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unsigned NumVals = TLI.getNumRegisters(VT);
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N = DAG.getCopyFromReg(DAG.getEntryNode(), InReg, DestVT);
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if (NumVals == 1)
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N = DAG.getNode(ISD::BIT_CONVERT, VT, N);
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@ -3185,7 +3185,7 @@ GetRegistersForValue(AsmOperandInfo &OpInfo, bool HasEarlyClobber,
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unsigned NumRegs = 1;
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if (OpInfo.ConstraintVT != MVT::Other)
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NumRegs = TLI.getNumElements(OpInfo.ConstraintVT);
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NumRegs = TLI.getNumRegisters(OpInfo.ConstraintVT);
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MVT::ValueType RegVT;
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MVT::ValueType ValueVT = OpInfo.ConstraintVT;
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@ -3831,7 +3831,7 @@ TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
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// integers. Figure out what the destination type is and how many small
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// integers it turns into.
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MVT::ValueType NVT = getTypeToExpandTo(VT);
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unsigned NumVals = getNumElements(VT);
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unsigned NumVals = getNumRegisters(VT);
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for (unsigned i = 0; i != NumVals; ++i) {
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RetVals.push_back(NVT);
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// if it isn't first piece, alignment must be 1
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@ -4088,7 +4088,7 @@ TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
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// integers. Figure out what the source elt type is and how many small
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// integers it is.
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MVT::ValueType NVT = getTypeToExpandTo(VT);
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unsigned NumVals = getNumElements(VT);
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unsigned NumVals = getNumRegisters(VT);
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for (unsigned i = 0; i != NumVals; ++i)
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RetTys.push_back(NVT);
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} else {
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@ -4507,7 +4507,7 @@ SDOperand SelectionDAGLowering::CopyValueToVirtualRegister(Value *V,
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return DAG.getCopyToReg(getRoot(), Reg, Op);
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} else {
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DestVT = TLI.getTypeToExpandTo(SrcVT);
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unsigned NumVals = TLI.getNumElements(SrcVT);
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unsigned NumVals = TLI.getNumRegisters(SrcVT);
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if (NumVals == 1)
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return DAG.getCopyToReg(getRoot(), Reg,
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DAG.getNode(ISD::BIT_CONVERT, DestVT, Op));
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@ -4695,16 +4695,16 @@ void SelectionDAGISel::BuildSelectionDAG(SelectionDAG &DAG, BasicBlock *LLVMBB,
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// Remember that this register needs to added to the machine PHI node as
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// the input for this MBB.
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MVT::ValueType VT = TLI.getValueType(PN->getType());
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unsigned NumElements;
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unsigned NumRegisters;
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if (VT != MVT::Vector)
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NumElements = TLI.getNumElements(VT);
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NumRegisters = TLI.getNumRegisters(VT);
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else {
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MVT::ValueType VT1,VT2;
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NumElements =
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NumRegisters =
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TLI.getVectorTypeBreakdown(cast<VectorType>(PN->getType()),
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VT1, VT2);
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}
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for (unsigned i = 0, e = NumElements; i != e; ++i)
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for (unsigned i = 0, e = NumRegisters; i != e; ++i)
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PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
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}
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}
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@ -216,7 +216,7 @@ void TargetLowering::computeRegisterProperties() {
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// Everything defaults to one.
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for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i)
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NumElementsForVT[i] = 1;
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NumRegistersForVT[i] = 1;
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// Find the largest integer register class.
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unsigned LargestIntReg = MVT::i128;
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@ -227,12 +227,12 @@ void TargetLowering::computeRegisterProperties() {
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// many registers to represent as the previous ValueType.
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unsigned ExpandedReg = LargestIntReg; ++LargestIntReg;
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for (++ExpandedReg; MVT::isInteger((MVT::ValueType)ExpandedReg);++ExpandedReg)
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NumElementsForVT[ExpandedReg] = 2*NumElementsForVT[ExpandedReg-1];
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NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1];
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// Inspect all of the ValueType's possible, deciding how to process them.
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for (unsigned IntReg = MVT::i1; IntReg <= MVT::i128; ++IntReg)
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// If we are expanding this type, expand it!
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if (getNumElements((MVT::ValueType)IntReg) != 1)
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if (getNumRegisters((MVT::ValueType)IntReg) != 1)
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SetValueTypeAction((MVT::ValueType)IntReg, Expand, *this, TransformToType,
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ValueTypeActions);
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else if (!isTypeLegal((MVT::ValueType)IntReg))
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@ -250,7 +250,7 @@ void TargetLowering::computeRegisterProperties() {
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if (isTypeLegal(MVT::f64))
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TransformToType[MVT::f64] = MVT::f64;
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else {
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NumElementsForVT[MVT::f64] = NumElementsForVT[MVT::i64];
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NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64];
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SetValueTypeAction(MVT::f64, Expand, *this, TransformToType,
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ValueTypeActions);
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}
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@ -260,7 +260,7 @@ void TargetLowering::computeRegisterProperties() {
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SetValueTypeAction(MVT::f32, Promote, *this, TransformToType,
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ValueTypeActions);
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else {
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NumElementsForVT[MVT::f32] = NumElementsForVT[MVT::i32];
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NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32];
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SetValueTypeAction(MVT::f32, Expand, *this, TransformToType,
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ValueTypeActions);
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}
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