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[x86] Add vector @llvm.ctpop intrinsic custom lowering
Currently, when ctpop is supported for scalar types, the expansion of @llvm.ctpop.vXiY uses vector element extractions, insertions and individual calls to @llvm.ctpop.iY. When not, expansion with bit-math operations is used for the scalar calls. Local haswell measurements show that we can improve vector @llvm.ctpop.vXiY expansion in some cases by using a using a vector parallel bit twiddling approach, based on: v = v - ((v >> 1) & 0x55555555); v = (v & 0x33333333) + ((v >> 2) & 0x33333333); v = ((v + (v >> 4) & 0xF0F0F0F) v = v + (v >> 8) v = v + (v >> 16) v = v & 0x0000003F (from http://graphics.stanford.edu/~seander/bithacks.html#CountBitsSetParallel) When scalar ctpop isn't supported, the approach above performs better for v2i64, v4i32, v4i64 and v8i32 (see numbers below). And even when scalar ctpop is supported, this approach performs ~2x better for v8i32. Here, x86_64 implies -march=corei7-avx without ctpop and x86_64h includes ctpop support with -march=core-avx2. == [x86_64h - new] v8i32: 0.661685 v4i32: 0.514678 v4i64: 0.652009 v2i64: 0.324289 == [x86_64h - old] v8i32: 1.29578 v4i32: 0.528807 v4i64: 0.65981 v2i64: 0.330707 == [x86_64 - new] v8i32: 1.003 v4i32: 0.656273 v4i64: 1.11711 v2i64: 0.754064 == [x86_64 - old] v8i32: 2.34886 v4i32: 1.72053 v4i64: 1.41086 v2i64: 1.0244 More work for other vector types will come next. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224725 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bruno Cardoso Lopes
parent
ddba295642
commit
ba059464c3
@ -987,6 +987,14 @@ void X86TargetLowering::resetOperationActions() {
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setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
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setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
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// Only provide customized ctpop vector bit twiddling for vector types we
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// know to perform better than using the popcnt instructions on each vector
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// element. If popcnt isn't supported, always provide the custom version.
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if (!Subtarget->hasPOPCNT()) {
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setOperationAction(ISD::CTPOP, MVT::v4i32, Custom);
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setOperationAction(ISD::CTPOP, MVT::v2i64, Custom);
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}
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// Custom lower build_vector, vector_shuffle, and extract_vector_elt.
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for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
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MVT VT = (MVT::SimpleValueType)i;
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@ -1282,6 +1290,16 @@ void X86TargetLowering::resetOperationActions() {
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// The custom lowering for UINT_TO_FP for v8i32 becomes interesting
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// when we have a 256bit-wide blend with immediate.
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setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Custom);
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// Only provide customized ctpop vector bit twiddling for vector types we
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// know to perform better than using the popcnt instructions on each
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// vector element. If popcnt isn't supported, always provide the custom
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// version.
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if (!Subtarget->hasPOPCNT())
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setOperationAction(ISD::CTPOP, MVT::v4i64, Custom);
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// Custom CTPOP always performs better on natively supported v8i32
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setOperationAction(ISD::CTPOP, MVT::v8i32, Custom);
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} else {
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setOperationAction(ISD::ADD, MVT::v4i64, Custom);
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setOperationAction(ISD::ADD, MVT::v8i32, Custom);
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@ -19183,6 +19201,139 @@ static SDValue LowerBITCAST(SDValue Op, const X86Subtarget *Subtarget,
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return SDValue();
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}
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static SDValue LowerCTPOP(SDValue Op, const X86Subtarget *Subtarget,
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SelectionDAG &DAG) {
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SDNode *Node = Op.getNode();
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SDLoc dl(Node);
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Op = Op.getOperand(0);
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EVT VT = Op.getValueType();
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assert((VT.is128BitVector() || VT.is256BitVector()) &&
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"CTPOP lowering only implemented for 128/256-bit wide vector types");
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unsigned NumElts = VT.getVectorNumElements();
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EVT EltVT = VT.getVectorElementType();
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unsigned Len = EltVT.getSizeInBits();
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// This is the vectorized version of the "best" algorithm from
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// http://graphics.stanford.edu/~seander/bithacks.html#CountBitsSetParallel
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// with a minor tweak to use a series of adds + shifts instead of vector
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// multiplications. Implemented for the v2i64, v4i64, v4i32, v8i32 types:
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//
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// v2i64, v4i64, v4i32 => Only profitable w/ popcnt disabled
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// v8i32 => Always profitable
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//
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// FIXME: There a couple of possible improvements:
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//
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// 1) Support for i8 and i16 vectors (needs measurements if popcnt enabled).
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// 2) Use strategies from http://wm.ite.pl/articles/sse-popcount.html
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//
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assert(EltVT.isInteger() && (Len == 32 || Len == 64) && Len % 8 == 0 &&
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"CTPOP not implemented for this vector element type.");
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// X86 canonicalize ANDs to vXi64, generate the appropriate bitcasts to avoid
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// extra legalization.
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bool NeedsBitcast = EltVT == MVT::i32;
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MVT BitcastVT = VT.is256BitVector() ? MVT::v4i64 : MVT::v2i64;
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SDValue Cst55 = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x55)), EltVT);
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SDValue Cst33 = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x33)), EltVT);
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SDValue Cst0F = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x0F)), EltVT);
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// v = v - ((v >> 1) & 0x55555555...)
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SmallVector<SDValue, 8> Ones(NumElts, DAG.getConstant(1, EltVT));
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SDValue OnesV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ones);
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SDValue Srl = DAG.getNode(ISD::SRL, dl, VT, Op, OnesV);
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if (NeedsBitcast)
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Srl = DAG.getNode(ISD::BITCAST, dl, BitcastVT, Srl);
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SmallVector<SDValue, 8> Mask55(NumElts, Cst55);
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SDValue M55 = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Mask55);
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if (NeedsBitcast)
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M55 = DAG.getNode(ISD::BITCAST, dl, BitcastVT, M55);
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SDValue And = DAG.getNode(ISD::AND, dl, Srl.getValueType(), Srl, M55);
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if (VT != And.getValueType())
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And = DAG.getNode(ISD::BITCAST, dl, VT, And);
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SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, Op, And);
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// v = (v & 0x33333333...) + ((v >> 2) & 0x33333333...)
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SmallVector<SDValue, 8> Mask33(NumElts, Cst33);
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SDValue M33 = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Mask33);
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SmallVector<SDValue, 8> Twos(NumElts, DAG.getConstant(2, EltVT));
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SDValue TwosV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Twos);
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Srl = DAG.getNode(ISD::SRL, dl, VT, Sub, TwosV);
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if (NeedsBitcast) {
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Srl = DAG.getNode(ISD::BITCAST, dl, BitcastVT, Srl);
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M33 = DAG.getNode(ISD::BITCAST, dl, BitcastVT, M33);
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Sub = DAG.getNode(ISD::BITCAST, dl, BitcastVT, Sub);
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}
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SDValue AndRHS = DAG.getNode(ISD::AND, dl, M33.getValueType(), Srl, M33);
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SDValue AndLHS = DAG.getNode(ISD::AND, dl, M33.getValueType(), Sub, M33);
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if (VT != AndRHS.getValueType()) {
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AndRHS = DAG.getNode(ISD::BITCAST, dl, VT, AndRHS);
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AndLHS = DAG.getNode(ISD::BITCAST, dl, VT, AndLHS);
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}
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SDValue Add = DAG.getNode(ISD::ADD, dl, VT, AndLHS, AndRHS);
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// v = (v + (v >> 4)) & 0x0F0F0F0F...
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SmallVector<SDValue, 8> Fours(NumElts, DAG.getConstant(4, EltVT));
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SDValue FoursV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Fours);
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Srl = DAG.getNode(ISD::SRL, dl, VT, Add, FoursV);
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Add = DAG.getNode(ISD::ADD, dl, VT, Add, Srl);
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SmallVector<SDValue, 8> Mask0F(NumElts, Cst0F);
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SDValue M0F = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Mask0F);
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if (NeedsBitcast) {
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Add = DAG.getNode(ISD::BITCAST, dl, BitcastVT, Add);
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M0F = DAG.getNode(ISD::BITCAST, dl, BitcastVT, M0F);
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}
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And = DAG.getNode(ISD::AND, dl, M0F.getValueType(), Add, M0F);
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if (VT != And.getValueType())
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And = DAG.getNode(ISD::BITCAST, dl, VT, And);
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// The algorithm mentioned above uses:
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// v = (v * 0x01010101...) >> (Len - 8)
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//
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// Change it to use vector adds + vector shifts which yield faster results on
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// Haswell than using vector integer multiplication.
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//
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// For i32 elements:
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// v = v + (v >> 8)
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// v = v + (v >> 16)
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//
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// For i64 elements:
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// v = v + (v >> 8)
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// v = v + (v >> 16)
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// v = v + (v >> 32)
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//
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Add = And;
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SmallVector<SDValue, 8> Csts;
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for (unsigned i = 8; i <= Len/2; i *= 2) {
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Csts.assign(NumElts, DAG.getConstant(i, EltVT));
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SDValue CstsV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Csts);
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Srl = DAG.getNode(ISD::SRL, dl, VT, Add, CstsV);
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Add = DAG.getNode(ISD::ADD, dl, VT, Add, Srl);
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Csts.clear();
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}
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// The result is on the least significant 6-bits on i32 and 7-bits on i64.
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SDValue Cst3F = DAG.getConstant(APInt(Len, Len == 32 ? 0x3F : 0x7F), EltVT);
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SmallVector<SDValue, 8> Cst3FV(NumElts, Cst3F);
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SDValue M3F = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Cst3FV);
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if (NeedsBitcast) {
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Add = DAG.getNode(ISD::BITCAST, dl, BitcastVT, Add);
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M3F = DAG.getNode(ISD::BITCAST, dl, BitcastVT, M3F);
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}
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And = DAG.getNode(ISD::AND, dl, M3F.getValueType(), Add, M3F);
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if (VT != And.getValueType())
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And = DAG.getNode(ISD::BITCAST, dl, VT, And);
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return And;
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}
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static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
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SDNode *Node = Op.getNode();
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SDLoc dl(Node);
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@ -19310,6 +19461,7 @@ SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
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case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
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case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
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return LowerCMP_SWAP(Op, Subtarget, DAG);
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case ISD::CTPOP: return LowerCTPOP(Op, Subtarget, DAG);
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case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
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case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
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case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
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159
test/CodeGen/X86/vector-ctpop.ll
Normal file
159
test/CodeGen/X86/vector-ctpop.ll
Normal file
@ -0,0 +1,159 @@
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; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=core-avx2 | FileCheck -check-prefix=AVX2 %s
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; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -mattr=-popcnt | FileCheck -check-prefix=AVX1-NOPOPCNT %s
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; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=core-avx2 -mattr=-popcnt | FileCheck -check-prefix=AVX2-NOPOPCNT %s
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; Vector version of:
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; v = v - ((v >> 1) & 0x55555555)
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; v = (v & 0x33333333) + ((v >> 2) & 0x33333333)
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; v = (v + (v >> 4) & 0xF0F0F0F)
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; v = v + (v >> 8)
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; v = v + (v >> 16)
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; v = v + (v >> 32) ; i64 only
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define <8 x i32> @test0(<8 x i32> %x) {
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; AVX2-LABEL: @test0
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entry:
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; AVX2: vpsrld $1, %ymm
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; AVX2-NEXT: vpbroadcastd
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; AVX2-NEXT: vpand
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; AVX2-NEXT: vpsubd
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; AVX2-NEXT: vpbroadcastd
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; AVX2-NEXT: vpand
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; AVX2-NEXT: vpsrld $2
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; AVX2-NEXT: vpand
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; AVX2-NEXT: vpaddd
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; AVX2-NEXT: vpsrld $4
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; AVX2-NEXT: vpaddd
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; AVX2-NEXT: vpbroadcastd
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; AVX2-NEXT: vpand
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; AVX2-NEXT: vpsrld $8
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; AVX2-NEXT: vpaddd
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; AVX2-NEXT: vpsrld $16
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; AVX2-NEXT: vpaddd
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; AVX2-NEXT: vpbroadcastd
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; AVX2-NEXT: vpand
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%y = call <8 x i32> @llvm.ctpop.v8i32(<8 x i32> %x)
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ret <8 x i32> %y
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}
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define <4 x i64> @test1(<4 x i64> %x) {
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; AVX2-NOPOPCNT-LABEL: @test1
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entry:
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; AVX2-NOPOPCNT: vpsrlq $1, %ymm
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; AVX2-NOPOPCNT-NEXT: vpbroadcastq
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; AVX2-NOPOPCNT-NEXT: vpand
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; AVX2-NOPOPCNT-NEXT: vpsubq
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; AVX2-NOPOPCNT-NEXT: vpbroadcastq
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; AVX2-NOPOPCNT-NEXT: vpand
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; AVX2-NOPOPCNT-NEXT: vpsrlq $2
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; AVX2-NOPOPCNT-NEXT: vpand
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; AVX2-NOPOPCNT-NEXT: vpaddq
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; AVX2-NOPOPCNT-NEXT: vpsrlq $4
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; AVX2-NOPOPCNT-NEXT: vpaddq
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; AVX2-NOPOPCNT-NEXT: vpbroadcastq
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; AVX2-NOPOPCNT-NEXT: vpand
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; AVX2-NOPOPCNT-NEXT: vpsrlq $8
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; AVX2-NOPOPCNT-NEXT: vpaddq
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; AVX2-NOPOPCNT-NEXT: vpsrlq $16
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; AVX2-NOPOPCNT-NEXT: vpaddq
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; AVX2-NOPOPCNT-NEXT: vpsrlq $32
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; AVX2-NOPOPCNT-NEXT: vpaddq
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; AVX2-NOPOPCNT-NEXT: vpbroadcastq
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; AVX2-NOPOPCNT-NEXT: vpand
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%y = call <4 x i64> @llvm.ctpop.v4i64(<4 x i64> %x)
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ret <4 x i64> %y
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}
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define <4 x i32> @test2(<4 x i32> %x) {
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; AVX2-NOPOPCNT-LABEL: @test2
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; AVX1-NOPOPCNT-LABEL: @test2
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entry:
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; AVX2-NOPOPCNT: vpsrld $1, %xmm
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; AVX2-NOPOPCNT-NEXT: vpbroadcastd
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; AVX2-NOPOPCNT-NEXT: vpand
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; AVX2-NOPOPCNT-NEXT: vpsubd
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; AVX2-NOPOPCNT-NEXT: vpbroadcastd
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; AVX2-NOPOPCNT-NEXT: vpand
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; AVX2-NOPOPCNT-NEXT: vpsrld $2
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; AVX2-NOPOPCNT-NEXT: vpand
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; AVX2-NOPOPCNT-NEXT: vpaddd
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; AVX2-NOPOPCNT-NEXT: vpsrld $4
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; AVX2-NOPOPCNT-NEXT: vpaddd
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; AVX2-NOPOPCNT-NEXT: vpbroadcastd
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; AVX2-NOPOPCNT-NEXT: vpand
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; AVX2-NOPOPCNT-NEXT: vpsrld $8
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; AVX2-NOPOPCNT-NEXT: vpaddd
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; AVX2-NOPOPCNT-NEXT: vpsrld $16
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; AVX2-NOPOPCNT-NEXT: vpaddd
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; AVX2-NOPOPCNT-NEXT: vpbroadcastd
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; AVX2-NOPOPCNT-NEXT: vpand
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; AVX1-NOPOPCNT: vpsrld $1, %xmm
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; AVX1-NOPOPCNT-NEXT: vpand
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; AVX1-NOPOPCNT-NEXT: vpsubd
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; AVX1-NOPOPCNT-NEXT: vmovdqa
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; AVX1-NOPOPCNT-NEXT: vpand
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; AVX1-NOPOPCNT-NEXT: vpsrld $2
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; AVX1-NOPOPCNT-NEXT: vpand
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; AVX1-NOPOPCNT-NEXT: vpaddd
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; AVX1-NOPOPCNT-NEXT: vpsrld $4
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; AVX1-NOPOPCNT-NEXT: vpaddd
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; AVX1-NOPOPCNT-NEXT: vpand
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; AVX1-NOPOPCNT-NEXT: vpsrld $8
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; AVX1-NOPOPCNT-NEXT: vpaddd
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; AVX1-NOPOPCNT-NEXT: vpsrld $16
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; AVX1-NOPOPCNT-NEXT: vpaddd
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; AVX1-NOPOPCNT-NEXT: vpand
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%y = call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %x)
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ret <4 x i32> %y
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}
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define <2 x i64> @test3(<2 x i64> %x) {
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; AVX2-NOPOPCNT-LABEL: @test3
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; AVX1-NOPOPCNT-LABEL: @test3
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entry:
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; AVX2-NOPOPCNT: vpsrlq $1, %xmm
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; AVX2-NOPOPCNT-NEXT: vpand
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; AVX2-NOPOPCNT-NEXT: vpsubq
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; AVX2-NOPOPCNT-NEXT: vmovdqa
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; AVX2-NOPOPCNT-NEXT: vpand
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; AVX2-NOPOPCNT-NEXT: vpsrlq $2
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; AVX2-NOPOPCNT-NEXT: vpand
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; AVX2-NOPOPCNT-NEXT: vpaddq
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; AVX2-NOPOPCNT-NEXT: vpsrlq $4
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; AVX2-NOPOPCNT-NEXT: vpaddq
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; AVX2-NOPOPCNT-NEXT: vpand
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; AVX2-NOPOPCNT-NEXT: vpsrlq $8
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; AVX2-NOPOPCNT-NEXT: vpaddq
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; AVX2-NOPOPCNT-NEXT: vpsrlq $16
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; AVX2-NOPOPCNT-NEXT: vpaddq
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; AVX2-NOPOPCNT-NEXT: vpsrlq $32
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; AVX2-NOPOPCNT-NEXT: vpaddq
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; AVX2-NOPOPCNT-NEXT: vpand
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; AVX1-NOPOPCNT: vpsrlq $1, %xmm
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; AVX1-NOPOPCNT-NEXT: vpand
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; AVX1-NOPOPCNT-NEXT: vpsubq
|
||||
; AVX1-NOPOPCNT-NEXT: vmovdqa
|
||||
; AVX1-NOPOPCNT-NEXT: vpand
|
||||
; AVX1-NOPOPCNT-NEXT: vpsrlq $2
|
||||
; AVX1-NOPOPCNT-NEXT: vpand
|
||||
; AVX1-NOPOPCNT-NEXT: vpaddq
|
||||
; AVX1-NOPOPCNT-NEXT: vpsrlq $4
|
||||
; AVX1-NOPOPCNT-NEXT: vpaddq
|
||||
; AVX1-NOPOPCNT-NEXT: vpand
|
||||
; AVX1-NOPOPCNT-NEXT: vpsrlq $8
|
||||
; AVX1-NOPOPCNT-NEXT: vpaddq
|
||||
; AVX1-NOPOPCNT-NEXT: vpsrlq $16
|
||||
; AVX1-NOPOPCNT-NEXT: vpaddq
|
||||
; AVX1-NOPOPCNT-NEXT: vpsrlq $32
|
||||
; AVX1-NOPOPCNT-NEXT: vpaddq
|
||||
; AVX1-NOPOPCNT-NEXT: vpand
|
||||
%y = call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %x)
|
||||
ret <2 x i64> %y
|
||||
}
|
||||
|
||||
declare <4 x i32> @llvm.ctpop.v4i32(<4 x i32>)
|
||||
declare <2 x i64> @llvm.ctpop.v2i64(<2 x i64>)
|
||||
|
||||
declare <8 x i32> @llvm.ctpop.v8i32(<8 x i32>)
|
||||
declare <4 x i64> @llvm.ctpop.v4i64(<4 x i64>)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user