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Add VirtRegMap::rewrite() and use it in the new register allocators.
The rewriter works almost identically to -rewriter=trivial, except it also eliminates any identity copies. This makes the new register allocators independent of VirtRegRewriter.cpp which will be going away at the same time as RegAllocLinearScan. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125967 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -18,7 +18,6 @@
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#include "RenderMachineFunction.h"
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#include "Spiller.h"
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#include "VirtRegMap.h"
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#include "VirtRegRewriter.h"
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#include "llvm/ADT/OwningPtr.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/Analysis/AliasAnalysis.h"
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@ -510,8 +509,7 @@ bool RABasic::runOnMachineFunction(MachineFunction &mf) {
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#endif // !NDEBUG
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// Run rewriter
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std::auto_ptr<VirtRegRewriter> rewriter(createVirtRegRewriter());
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rewriter->runOnMachineFunction(*MF, *VRM, LIS);
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VRM->rewrite(LIS->getSlotIndexes());
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// The pass output is in VirtRegMap. Release all the transient data.
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releaseMemory();
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@ -21,7 +21,6 @@
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#include "SpillPlacement.h"
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#include "SplitKit.h"
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#include "VirtRegMap.h"
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#include "VirtRegRewriter.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/Analysis/AliasAnalysis.h"
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#include "llvm/Function.h"
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@ -1273,8 +1272,7 @@ bool RAGreedy::runOnMachineFunction(MachineFunction &mf) {
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// Run rewriter
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{
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NamedRegionTimer T("Rewriter", TimerGroupName, TimePassesIsEnabled);
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std::auto_ptr<VirtRegRewriter> rewriter(createVirtRegRewriter());
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rewriter->runOnMachineFunction(*MF, *VRM, LIS);
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VRM->rewrite(Indexes);
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}
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// The pass output is in VirtRegMap. Release all the transient data.
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@ -24,6 +24,7 @@
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/SlotIndexes.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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@ -254,6 +255,76 @@ bool VirtRegMap::FindUnusedRegisters(LiveIntervals* LIs) {
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return AnyUnused;
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}
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void VirtRegMap::rewrite(SlotIndexes *Indexes) {
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DEBUG(dbgs() << "********** REWRITE VIRTUAL REGISTERS **********\n"
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<< "********** Function: "
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<< MF->getFunction()->getName() << '\n');
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SmallVector<unsigned, 8> SuperKills;
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for (MachineFunction::iterator MBBI = MF->begin(), MBBE = MF->end();
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MBBI != MBBE; ++MBBI) {
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DEBUG(MBBI->print(dbgs(), Indexes));
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for (MachineBasicBlock::iterator MII = MBBI->begin(), MIE = MBBI->end();
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MII != MIE;) {
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MachineInstr *MI = MII;
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++MII;
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for (MachineInstr::mop_iterator MOI = MI->operands_begin(),
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MOE = MI->operands_end(); MOI != MOE; ++MOI) {
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MachineOperand &MO = *MOI;
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if (!MO.isReg() || !TargetRegisterInfo::isVirtualRegister(MO.getReg()))
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continue;
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unsigned VirtReg = MO.getReg();
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unsigned PhysReg = getPhys(VirtReg);
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assert(PhysReg != NO_PHYS_REG && "Instruction uses unmapped VirtReg");
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// Preserve semantics of sub-register operands.
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if (MO.getSubReg()) {
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// A virtual register kill refers to the whole register, so we may
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// have to add <imp-use,kill> operands for the super-register.
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if (MO.isUse() && MO.isKill() && !MO.isUndef())
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SuperKills.push_back(PhysReg);
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// We don't have to deal with sub-register defs because
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// LiveIntervalAnalysis already added the necessary <imp-def>
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// operands.
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// PhysReg operands cannot have subregister indexes.
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PhysReg = TRI->getSubReg(PhysReg, MO.getSubReg());
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assert(PhysReg && "Invalid SubReg for physical register");
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MO.setSubReg(0);
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}
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// Rewrite. Note we could have used MachineOperand::substPhysReg(), but
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// we need the inlining here.
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MO.setReg(PhysReg);
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}
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// Add any missing super-register kills after rewriting the whole
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// instruction.
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while (!SuperKills.empty())
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MI->addRegisterKilled(SuperKills.pop_back_val(), TRI, true);
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DEBUG(dbgs() << "> " << *MI);
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// Finally, remove any identity copies.
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if (MI->isIdentityCopy()) {
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DEBUG(dbgs() << "Deleting identity copy.\n");
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RemoveMachineInstrFromMaps(MI);
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if (Indexes)
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Indexes->removeMachineInstrFromMaps(MI);
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// It's safe to erase MI because MII has already been incremented.
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MI->eraseFromParent();
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}
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}
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}
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// Tell MRI about physical registers in use.
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for (unsigned Reg = 1, RegE = TRI->getNumRegs(); Reg != RegE; ++Reg)
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if (!MRI->reg_nodbg_empty(Reg))
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MRI->setPhysRegUsed(Reg);
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}
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void VirtRegMap::print(raw_ostream &OS, const Module* M) const {
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const TargetRegisterInfo* TRI = MF->getTarget().getRegisterInfo();
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const MachineRegisterInfo &MRI = MF->getRegInfo();
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@ -35,6 +35,7 @@ namespace llvm {
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class TargetInstrInfo;
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class TargetRegisterInfo;
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class raw_ostream;
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class SlotIndexes;
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class VirtRegMap : public MachineFunctionPass {
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public:
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@ -493,6 +494,13 @@ namespace llvm {
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return 0;
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}
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/// rewrite - Rewrite all instructions in MF to use only physical registers
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/// by mapping all virtual register operands to their assigned physical
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/// registers.
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///
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/// @param Indexes Optionally remove deleted instructions from indexes.
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void rewrite(SlotIndexes *Indexes);
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void print(raw_ostream &OS, const Module* M = 0) const;
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void dump() const;
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};
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