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https://github.com/c64scene-ar/llvm-6502.git
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Transform: (EXTRACT_VECTOR_ELT( VECTOR_SHUFFLE )) -> EXTRACT_VECTOR_ELT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148337 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Nadav Rotem
parent
6220fea2a8
commit
ba05c91ed2
@ -6982,13 +6982,14 @@ SDValue DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) {
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SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) {
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// (vextract (scalar_to_vector val, 0) -> val
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SDValue InVec = N->getOperand(0);
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EVT VT = InVec.getValueType();
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EVT NVT = N->getValueType(0);
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if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) {
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// Check if the result type doesn't match the inserted element type. A
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// SCALAR_TO_VECTOR may truncate the inserted element and the
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// EXTRACT_VECTOR_ELT may widen the extracted vector.
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SDValue InOp = InVec.getOperand(0);
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EVT NVT = N->getValueType(0);
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if (InOp.getValueType() != NVT) {
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assert(InOp.getValueType().isInteger() && NVT.isInteger());
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return DAG.getSExtOrTrunc(InOp, InVec.getDebugLoc(), NVT);
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@ -6996,6 +6997,38 @@ SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) {
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return InOp;
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}
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SDValue EltNo = N->getOperand(1);
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bool ConstEltNo = isa<ConstantSDNode>(EltNo);
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// Transform: (EXTRACT_VECTOR_ELT( VECTOR_SHUFFLE )) -> EXTRACT_VECTOR_ELT.
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// We only perform this optimization before the op legalization phase because
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// we may introduce new vector instructions which are not backed by TD patterns.
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// For example on AVX, extracting elements from a wide vector without using
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// extract_subvector.
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if (InVec.getOpcode() == ISD::VECTOR_SHUFFLE
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&& ConstEltNo && !LegalOperations) {
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int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
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int NumElem = VT.getVectorNumElements();
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ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(InVec);
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// Find the new index to extract from.
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int OrigElt = SVOp->getMaskElt(Elt);
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// Extracting an undef index is undef.
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if (OrigElt == -1)
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return DAG.getUNDEF(NVT);
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// Select the right vector half to extract from.
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if (OrigElt < NumElem) {
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InVec = InVec->getOperand(0);
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} else {
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InVec = InVec->getOperand(1);
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OrigElt -= NumElem;
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}
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return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, N->getDebugLoc(), NVT,
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InVec, DAG.getConstant(OrigElt, MVT::i32));
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}
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// Perform only after legalization to ensure build_vector / vector_shuffle
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// optimizations have already been done.
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if (!LegalOperations) return SDValue();
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@ -7003,13 +7036,11 @@ SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) {
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// (vextract (v4f32 load $addr), c) -> (f32 load $addr+c*size)
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// (vextract (v4f32 s2v (f32 load $addr)), c) -> (f32 load $addr+c*size)
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// (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), 0) -> (f32 load $addr)
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SDValue EltNo = N->getOperand(1);
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if (isa<ConstantSDNode>(EltNo)) {
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if (ConstEltNo) {
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int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
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bool NewLoad = false;
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bool BCNumEltsChanged = false;
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EVT VT = InVec.getValueType();
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EVT ExtVT = VT.getVectorElementType();
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EVT LVT = ExtVT;
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@ -1,5 +1,5 @@
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; RUN: llc < %s -march=cellspu -o %t1.s
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; RUN: grep rot %t1.s | count 86
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; RUN: grep rot %t1.s | count 85
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; RUN: grep roth %t1.s | count 8
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; RUN: grep roti.*5 %t1.s | count 1
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; RUN: grep roti.*27 %t1.s | count 1
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@ -163,7 +163,7 @@ define i8 @rotri8(i8 %A) {
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define <2 x float> @test1(<4 x float> %param )
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{
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; CHECK: test1
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; CHECK: rotqbyi
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; CHECK: shufb
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%el = extractelement <4 x float> %param, i32 1
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%vec1 = insertelement <1 x float> undef, float %el, i32 0
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%rv = shufflevector <1 x float> %vec1, <1 x float> undef, <2 x i32><i32 0,i32 0>
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@ -12,11 +12,11 @@ define <4 x float> @test1(<4 x float> %a) nounwind {
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; rdar://10538417
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define <3 x i64> @test2(<2 x i64> %v) nounwind readnone {
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; CHECK: test2:
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; CHECK: vxorpd
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; CHECK: vperm2f128
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; CHECK: vinsertf128
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%1 = shufflevector <2 x i64> %v, <2 x i64> %v, <3 x i32> <i32 0, i32 1, i32 undef>
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%2 = shufflevector <3 x i64> zeroinitializer, <3 x i64> %1, <3 x i32> <i32 3, i32 4, i32 2>
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ret <3 x i64> %2
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; CHECK: ret
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}
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define <4 x i64> @test3(<4 x i64> %a, <4 x i64> %b) nounwind {
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@ -24,6 +24,7 @@ define <4 x i64> @test3(<4 x i64> %a, <4 x i64> %b) nounwind {
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ret <4 x i64> %c
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; CHECK: test3:
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; CHECK: vperm2f128
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; CHECK: ret
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}
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define <8 x float> @test4(float %a) nounwind {
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@ -75,3 +76,23 @@ entry:
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; CHECK: ret
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ret void
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}
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; Extract a value from a shufflevector..
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define i32 @test9(<4 x i32> %a) nounwind {
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; CHECK: test9
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; CHECK: vpextrd
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%b = shufflevector <4 x i32> %a, <4 x i32> undef, <8 x i32> <i32 1, i32 1, i32 2, i32 2, i32 3, i32 3, i32 undef, i32 4>
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%r = extractelement <8 x i32> %b, i32 2
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; CHECK: ret
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ret i32 %r
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}
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; Extract a value which is the result of an undef mask.
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define i32 @test10(<4 x i32> %a) nounwind {
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; CHECK: @test10
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; CHECK-NEXT: #
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; CHECK-NEXT: ret
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%b = shufflevector <4 x i32> %a, <4 x i32> undef, <8 x i32> <i32 1, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
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%r = extractelement <8 x i32> %b, i32 2
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ret i32 %r
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}
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@ -10,6 +10,7 @@ entry:
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%val = fadd <3 x float> %x, %src2
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store <3 x float> %val, <3 x float>* %dst.addr
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ret void
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; CHECK: ret
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}
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@ -23,6 +24,7 @@ entry:
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%val = fadd <3 x float> %x, %src2
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store <3 x float> %val, <3 x float>* %dst.addr
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ret void
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; CHECK: ret
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}
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; Example of when widening a v3float operation causes the DAG to replace a node
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@ -31,7 +33,7 @@ entry:
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define void @shuf3(<4 x float> %tmp10, <4 x float> %vecinit15, <4 x float>* %dst) nounwind {
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entry:
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; CHECK: shuf3:
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; CHECK: pshufd
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; CHECK: shufps
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%shuffle.i.i.i12 = shufflevector <4 x float> %tmp10, <4 x float> %vecinit15, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
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%tmp25.i.i = shufflevector <4 x float> %shuffle.i.i.i12, <4 x float> undef, <3 x i32> <i32 0, i32 1, i32 2>
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%tmp1.i.i = shufflevector <3 x float> %tmp25.i.i, <3 x float> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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@ -45,6 +47,7 @@ entry:
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%shuffle.i.i.i21 = shufflevector <4 x float> %tmp2.i18, <4 x float> undef, <4 x i32> <i32 2, i32 3, i32 2, i32 3>
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store <4 x float> %shuffle.i.i.i21, <4 x float>* %dst
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ret void
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; CHECK: ret
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}
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; PR10421: make sure we correctly handle extreme widening with CONCAT_VECTORS
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@ -53,6 +56,7 @@ define <8 x i8> @shuf4(<4 x i8> %a, <4 x i8> %b) nounwind readnone {
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; CHECK-NOT: punpckldq
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%vshuf = shufflevector <4 x i8> %a, <4 x i8> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
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ret <8 x i8> %vshuf
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; CHECK: ret
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}
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; PR11389: another CONCAT_VECTORS case
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@ -61,4 +65,5 @@ define void @shuf5(<8 x i8>* %p) nounwind {
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%v = shufflevector <2 x i8> <i8 4, i8 33>, <2 x i8> undef, <8 x i32> <i32 1, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
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store <8 x i8> %v, <8 x i8>* %p, align 8
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ret void
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; CHECK: ret
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}
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