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Generic expansion for atomic load/store into cmpxchg/atomicrmw xchg; implements 64-bit atomic load/store for ARM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138872 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1057,6 +1057,7 @@ void DAGTypeLegalizer::ExpandIntegerResult(SDNode *N, unsigned ResNo) {
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case ISD::UDIV: ExpandIntRes_UDIV(N, Lo, Hi); break;
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case ISD::UREM: ExpandIntRes_UREM(N, Lo, Hi); break;
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case ISD::ZERO_EXTEND: ExpandIntRes_ZERO_EXTEND(N, Lo, Hi); break;
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case ISD::ATOMIC_LOAD: ExpandIntRes_ATOMIC_LOAD(N, Lo, Hi); break;
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case ISD::ATOMIC_LOAD_ADD:
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case ISD::ATOMIC_LOAD_SUB:
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@ -2323,6 +2324,20 @@ void DAGTypeLegalizer::ExpandIntRes_ZERO_EXTEND(SDNode *N,
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}
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}
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void DAGTypeLegalizer::ExpandIntRes_ATOMIC_LOAD(SDNode *N,
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SDValue &Lo, SDValue &Hi) {
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DebugLoc dl = N->getDebugLoc();
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EVT VT = cast<AtomicSDNode>(N)->getMemoryVT();
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SDValue Zero = DAG.getConstant(0, VT);
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SDValue Swap = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl, VT,
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N->getOperand(0),
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N->getOperand(1), Zero, Zero,
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cast<AtomicSDNode>(N)->getMemOperand(),
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cast<AtomicSDNode>(N)->getOrdering(),
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cast<AtomicSDNode>(N)->getSynchScope());
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ReplaceValueWith(SDValue(N, 0), Swap.getValue(0));
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ReplaceValueWith(SDValue(N, 1), Swap.getValue(1));
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}
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//===----------------------------------------------------------------------===//
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// Integer Operand Expansion
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@ -2367,6 +2382,8 @@ bool DAGTypeLegalizer::ExpandIntegerOperand(SDNode *N, unsigned OpNo) {
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case ISD::ROTR: Res = ExpandIntOp_Shift(N); break;
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case ISD::RETURNADDR:
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case ISD::FRAMEADDR: Res = ExpandIntOp_RETURNADDR(N); break;
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case ISD::ATOMIC_STORE: Res = ExpandIntOp_ATOMIC_STORE(N); break;
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}
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// If the result is null, the sub-method took care of registering results etc.
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@ -2744,6 +2761,19 @@ SDValue DAGTypeLegalizer::ExpandIntOp_UINT_TO_FP(SDNode *N) {
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return MakeLibCall(LC, DstVT, &Op, 1, true, dl);
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}
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SDValue DAGTypeLegalizer::ExpandIntOp_ATOMIC_STORE(SDNode *N) {
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DebugLoc dl = N->getDebugLoc();
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SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
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cast<AtomicSDNode>(N)->getMemoryVT(),
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N->getOperand(0),
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N->getOperand(1), N->getOperand(2),
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cast<AtomicSDNode>(N)->getMemOperand(),
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cast<AtomicSDNode>(N)->getOrdering(),
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cast<AtomicSDNode>(N)->getSynchScope());
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return Swap.getValue(1);
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}
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SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_SUBVECTOR(SDNode *N) {
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SDValue InOp0 = N->getOperand(0);
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EVT InVT = InOp0.getValueType();
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@ -320,6 +320,8 @@ private:
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void ExpandIntRes_UADDSUBO (SDNode *N, SDValue &Lo, SDValue &Hi);
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void ExpandIntRes_XMULO (SDNode *N, SDValue &Lo, SDValue &Hi);
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void ExpandIntRes_ATOMIC_LOAD (SDNode *N, SDValue &Lo, SDValue &Hi);
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void ExpandShiftByConstant(SDNode *N, unsigned Amt,
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SDValue &Lo, SDValue &Hi);
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bool ExpandShiftWithKnownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi);
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@ -339,6 +341,7 @@ private:
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SDValue ExpandIntOp_TRUNCATE(SDNode *N);
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SDValue ExpandIntOp_UINT_TO_FP(SDNode *N);
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SDValue ExpandIntOp_RETURNADDR(SDNode *N);
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SDValue ExpandIntOp_ATOMIC_STORE(SDNode *N);
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void IntegerExpandSetCCOperands(SDValue &NewLHS, SDValue &NewRHS,
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ISD::CondCode &CCCode, DebugLoc dl);
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@ -6,7 +6,7 @@ define i64 @test1(i64* %ptr, i64 %val) {
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; CHECK: ldrexd r2, r3
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; CHECK: adds r0, r2
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; CHECK: adc r1, r3
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; CHECK: strexd {{r[0-9]+}}, r0, r1
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; CHECK: strexd {{[a-z0-9]+}}, r0, r1
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; CHECK: cmp
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; CHECK: bne
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; CHECK: dmb ish
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@ -20,7 +20,7 @@ define i64 @test2(i64* %ptr, i64 %val) {
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; CHECK: ldrexd r2, r3
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; CHECK: subs r0, r2
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; CHECK: sbc r1, r3
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; CHECK: strexd {{r[0-9]+}}, r0, r1
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; CHECK: strexd {{[a-z0-9]+}}, r0, r1
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; CHECK: cmp
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; CHECK: bne
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; CHECK: dmb ish
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@ -34,7 +34,7 @@ define i64 @test3(i64* %ptr, i64 %val) {
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; CHECK: ldrexd r2, r3
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; CHECK: and r0, r2
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; CHECK: and r1, r3
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; CHECK: strexd {{r[0-9]+}}, r0, r1
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; CHECK: strexd {{[a-z0-9]+}}, r0, r1
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; CHECK: cmp
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; CHECK: bne
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; CHECK: dmb ish
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@ -48,7 +48,7 @@ define i64 @test4(i64* %ptr, i64 %val) {
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; CHECK: ldrexd r2, r3
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; CHECK: orr r0, r2
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; CHECK: orr r1, r3
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; CHECK: strexd {{r[0-9]+}}, r0, r1
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; CHECK: strexd {{[a-z0-9]+}}, r0, r1
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; CHECK: cmp
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; CHECK: bne
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; CHECK: dmb ish
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@ -62,7 +62,7 @@ define i64 @test5(i64* %ptr, i64 %val) {
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; CHECK: ldrexd r2, r3
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; CHECK: eor r0, r2
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; CHECK: eor r1, r3
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; CHECK: strexd {{r[0-9]+}}, r0, r1
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; CHECK: strexd {{[a-z0-9]+}}, r0, r1
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; CHECK: cmp
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; CHECK: bne
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; CHECK: dmb ish
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@ -74,7 +74,7 @@ define i64 @test6(i64* %ptr, i64 %val) {
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; CHECK: test6
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; CHECK: dmb ish
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; CHECK: ldrexd r2, r3
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; CHECK: strexd {{r[0-9]+}}, r0, r1
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; CHECK: strexd {{[a-z0-9]+}}, r0, r1
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; CHECK: cmp
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; CHECK: bne
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; CHECK: dmb ish
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@ -89,10 +89,40 @@ define i64 @test7(i64* %ptr, i64 %val1, i64 %val2) {
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; CHECK: cmp r2
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; CHECK: cmpeq r3
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; CHECK: bne
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; CHECK: strexd {{r[0-9]+}}, r0, r1
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; CHECK: strexd {{[a-z0-9]+}}, r0, r1
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; CHECK: cmp
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; CHECK: bne
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; CHECK: dmb ish
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%r = cmpxchg i64* %ptr, i64 %val1, i64 %val2 seq_cst
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ret i64 %r
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}
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; Compiles down to cmpxchg
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; FIXME: Should compile to a single ldrexd
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define i64 @test8(i64* %ptr) {
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; CHECK: test8
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; CHECK: ldrexd r2, r3
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; CHECK: cmp r2
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; CHECK: cmpeq r3
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; CHECK: bne
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; CHECK: strexd {{[a-z0-9]+}}, r0, r1
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; CHECK: cmp
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; CHECK: bne
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; CHECK: dmb ish
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%r = load atomic i64* %ptr seq_cst, align 8
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ret i64 %r
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}
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; Compiles down to atomicrmw xchg; there really isn't any more efficient
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; way to write it.
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define void @test9(i64* %ptr, i64 %val) {
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; CHECK: test9
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; CHECK: dmb ish
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; CHECK: ldrexd r2, r3
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; CHECK: strexd {{[a-z0-9]+}}, r0, r1
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; CHECK: cmp
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; CHECK: bne
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; CHECK: dmb ish
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store atomic i64 %val, i64* %ptr seq_cst, align 8
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ret void
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}
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