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Specify S registers as D registers' sub-registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36280 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -13,10 +13,10 @@
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//===----------------------------------------------------------------------===//
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// Registers are identified with 4-bit ID numbers.
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class ARMReg<bits<4> num, string n, list<Register> aliases = []> : Register<n> {
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class ARMReg<bits<4> num, string n, list<Register> subregs = []> : Register<n> {
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field bits<4> Num;
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let Namespace = "ARM";
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let Aliases = aliases;
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let SubRegs = subregs;
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}
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class ARMFReg<bits<5> num, string n> : Register<n> {
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