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[mips][msa] Add copy_{u,s}.d.

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These instructions are only available on Mips64 cores
that implement the MSA ASE.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200398 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Matheus Almeida
2014-01-29 14:05:28 +00:00
parent cf78698270
commit ba67c2a4ee
5 changed files with 92 additions and 14 deletions
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17
lib/Target/Mips/MipsMSAInstrFormats.td
View File

@@ -15,6 +15,10 @@ class MSAInst : MipsInst<(outs), (ins), "", [], NoItinerary, FrmOther> {
let Inst{31-26} = 0b011110;
}
class MSA64Inst : MSAInst {
let Predicates = [HasMSA, HasMips64];
}
class MSACBranch : MSAInst {
let Inst{31-26} = 0b010001;
}
@@ -274,6 +278,19 @@ class MSA_ELM_COPY_W_FMT<bits<4> major, bits<6> minor>: MSAInst {
let Inst{5-0} = minor;
}
class MSA_ELM_COPY_D_FMT<bits<4> major, bits<6> minor>: MSA64Inst {
bits<4> n;
bits<5> ws;
bits<5> rd;
let Inst{25-22} = major;
let Inst{21-17} = 0b11100;
let Inst{16} = n{0};
let Inst{15-11} = ws;
let Inst{10-6} = rd;
let Inst{5-0} = minor;
}
class MSA_ELM_INSERT_B_FMT<bits<4> major, bits<6> minor>: MSAInst {
bits<6> n;
bits<5> rs;

12
lib/Target/Mips/MipsMSAInstrInfo.td
View File

@@ -137,6 +137,8 @@ def vextract_sext_i16 : PatFrag<(ops node:$vec, node:$idx),
(MipsVExtractSExt node:$vec, node:$idx, i16)>;
def vextract_sext_i32 : PatFrag<(ops node:$vec, node:$idx),
(MipsVExtractSExt node:$vec, node:$idx, i32)>;
def vextract_sext_i64 : PatFrag<(ops node:$vec, node:$idx),
(MipsVExtractSExt node:$vec, node:$idx, i64)>;
def vextract_zext_i8 : PatFrag<(ops node:$vec, node:$idx),
(MipsVExtractZExt node:$vec, node:$idx, i8)>;
@@ -144,6 +146,8 @@ def vextract_zext_i16 : PatFrag<(ops node:$vec, node:$idx),
(MipsVExtractZExt node:$vec, node:$idx, i16)>;
def vextract_zext_i32 : PatFrag<(ops node:$vec, node:$idx),
(MipsVExtractZExt node:$vec, node:$idx, i32)>;
def vextract_zext_i64 : PatFrag<(ops node:$vec, node:$idx),
(MipsVExtractZExt node:$vec, node:$idx, i64)>;
def vinsert_v16i8 : PatFrag<(ops node:$vec, node:$val, node:$idx),
(v16i8 (vector_insert node:$vec, node:$val, node:$idx))>;
@@ -614,10 +618,12 @@ class CLTI_U_D_ENC : MSA_I5_FMT<0b011, 0b11, 0b000111>;
class COPY_S_B_ENC : MSA_ELM_COPY_B_FMT<0b0010, 0b011001>;
class COPY_S_H_ENC : MSA_ELM_COPY_H_FMT<0b0010, 0b011001>;
class COPY_S_W_ENC : MSA_ELM_COPY_W_FMT<0b0010, 0b011001>;
class COPY_S_D_ENC : MSA_ELM_COPY_D_FMT<0b0010, 0b011001>;
class COPY_U_B_ENC : MSA_ELM_COPY_B_FMT<0b0011, 0b011001>;
class COPY_U_H_ENC : MSA_ELM_COPY_H_FMT<0b0011, 0b011001>;
class COPY_U_W_ENC : MSA_ELM_COPY_W_FMT<0b0011, 0b011001>;
class COPY_U_D_ENC : MSA_ELM_COPY_D_FMT<0b0011, 0b011001>;
class CTCMSA_ENC : MSA_ELM_CTCMSA_FMT<0b0000111110, 0b011001>;
@@ -1877,6 +1883,8 @@ class COPY_S_H_DESC : MSA_COPY_DESC_BASE<"copy_s.h", vextract_sext_i16, v8i16,
GPR32Opnd, MSA128HOpnd>;
class COPY_S_W_DESC : MSA_COPY_DESC_BASE<"copy_s.w", vextract_sext_i32, v4i32,
GPR32Opnd, MSA128WOpnd>;
class COPY_S_D_DESC : MSA_COPY_DESC_BASE<"copy_s.d", vextract_sext_i64, v2i64,
GPR64Opnd, MSA128DOpnd>;
class COPY_U_B_DESC : MSA_COPY_DESC_BASE<"copy_u.b", vextract_zext_i8, v16i8,
GPR32Opnd, MSA128BOpnd>;
@@ -1884,6 +1892,8 @@ class COPY_U_H_DESC : MSA_COPY_DESC_BASE<"copy_u.h", vextract_zext_i16, v8i16,
GPR32Opnd, MSA128HOpnd>;
class COPY_U_W_DESC : MSA_COPY_DESC_BASE<"copy_u.w", vextract_zext_i32, v4i32,
GPR32Opnd, MSA128WOpnd>;
class COPY_U_D_DESC : MSA_COPY_DESC_BASE<"copy_u.d", vextract_zext_i64, v2i64,
GPR64Opnd, MSA128DOpnd>;
class COPY_FW_PSEUDO_DESC : MSA_COPY_PSEUDO_BASE<vector_extract, v4f32, FGR32,
MSA128W>;
@@ -2898,10 +2908,12 @@ def CLTI_U_D : CLTI_U_D_ENC, CLTI_U_D_DESC;
def COPY_S_B : COPY_S_B_ENC, COPY_S_B_DESC;
def COPY_S_H : COPY_S_H_ENC, COPY_S_H_DESC;
def COPY_S_W : COPY_S_W_ENC, COPY_S_W_DESC;
def COPY_S_D : COPY_S_D_ENC, COPY_S_D_DESC;
def COPY_U_B : COPY_U_B_ENC, COPY_U_B_DESC;
def COPY_U_H : COPY_U_H_ENC, COPY_U_H_DESC;
def COPY_U_W : COPY_U_W_ENC, COPY_U_W_DESC;
def COPY_U_D : COPY_U_D_ENC, COPY_U_D_DESC;
def COPY_FW_PSEUDO : COPY_FW_PSEUDO_DESC;
def COPY_FD_PSEUDO : COPY_FD_PSEUDO_DESC;

37
lib/Target/Mips/MipsSEISelLowering.cpp
View File

@@ -1616,25 +1616,34 @@ SDValue MipsSETargetLowering::lowerINTRINSIC_WO_CHAIN(SDValue Op,
case Intrinsic::mips_copy_s_w:
return lowerMSACopyIntr(Op, DAG, MipsISD::VEXTRACT_SEXT_ELT);
case Intrinsic::mips_copy_s_d:
// Don't lower directly into VEXTRACT_SEXT_ELT since i64 might be illegal.
// Instead lower to the generic EXTRACT_VECTOR_ELT node and let the type
// legalizer and EXTRACT_VECTOR_ELT lowering sort it out.
return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(Op), Op->getValueType(0),
Op->getOperand(1), Op->getOperand(2));
if (HasMips64)
// Lower directly into VEXTRACT_SEXT_ELT since i64 is legal on Mips64.
return lowerMSACopyIntr(Op, DAG, MipsISD::VEXTRACT_SEXT_ELT);
else {
// Lower into the generic EXTRACT_VECTOR_ELT node and let the type
// legalizer and EXTRACT_VECTOR_ELT lowering sort it out.
return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(Op),
Op->getValueType(0), Op->getOperand(1),
Op->getOperand(2));
}
case Intrinsic::mips_copy_u_b:
case Intrinsic::mips_copy_u_h:
case Intrinsic::mips_copy_u_w:
return lowerMSACopyIntr(Op, DAG, MipsISD::VEXTRACT_ZEXT_ELT);
case Intrinsic::mips_copy_u_d:
// Don't lower directly into VEXTRACT_ZEXT_ELT since i64 might be illegal.
// Instead lower to the generic EXTRACT_VECTOR_ELT node and let the type
// legalizer and EXTRACT_VECTOR_ELT lowering sort it out.
//
// Note: When i64 is illegal, this results in copy_s.w instructions instead
// of copy_u.w instructions. This makes no difference to the behaviour
// since i64 is only illegal when the register file is 32-bit.
return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(Op), Op->getValueType(0),
Op->getOperand(1), Op->getOperand(2));
if (HasMips64)
// Lower directly into VEXTRACT_ZEXT_ELT since i64 is legal on Mips64.
return lowerMSACopyIntr(Op, DAG, MipsISD::VEXTRACT_ZEXT_ELT);
else {
// Lower into the generic EXTRACT_VECTOR_ELT node and let the type
// legalizer and EXTRACT_VECTOR_ELT lowering sort it out.
// Note: When i64 is illegal, this results in copy_s.w instructions
// instead of copy_u.w instructions. This makes no difference to the
// behaviour since i64 is only illegal when the register file is 32-bit.
return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(Op),
Op->getValueType(0), Op->getOperand(1),
Op->getOperand(2));
}
case Intrinsic::mips_div_s_b:
case Intrinsic::mips_div_s_h:
case Intrinsic::mips_div_s_w: