mirror of
https://github.com/c64scene-ar/llvm-6502.git
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Remove some of the special classes that worked around an old tablegen limitation of not being able to remove redundant bitconverts from patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145003 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Craig Topper
parent
98fc72940b
commit
ba798c5e51
@ -3423,47 +3423,6 @@ multiclass PDI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
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[(set RC:$dst, (OpVT (OpNode RC:$src1,
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(bitconvert (memop_frag addr:$src2)))))]>;
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}
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/// PDI_binop_rm_v2i64 - Simple SSE2 binary operator whose type is v2i64.
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///
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/// FIXME: we could eliminate this and use PDI_binop_rm instead if tblgen knew
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/// to collapse (bitconvert VT to VT) into its operand.
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///
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multiclass PDI_binop_rm_v2i64<bits<8> opc, string OpcodeStr, SDNode OpNode,
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bit IsCommutable = 0, bit Is2Addr = 1> {
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let isCommutable = IsCommutable in
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def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
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(ins VR128:$src1, VR128:$src2),
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!if(Is2Addr,
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!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
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!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
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[(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))]>;
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def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
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(ins VR128:$src1, i128mem:$src2),
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!if(Is2Addr,
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!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
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!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
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[(set VR128:$dst, (OpNode VR128:$src1, (memopv2i64 addr:$src2)))]>;
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}
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/// PDI_binop_rm_v4i64 - Simple AVX2 binary operator whose type is v4i64.
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///
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/// FIXME: we could eliminate this and use PDI_binop_rm instead if tblgen knew
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/// to collapse (bitconvert VT to VT) into its operand.
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///
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multiclass PDI_binop_rm_v4i64<bits<8> opc, string OpcodeStr, SDNode OpNode,
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bit IsCommutable = 0> {
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let isCommutable = IsCommutable in
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def rr : PDI<opc, MRMSrcReg, (outs VR256:$dst),
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(ins VR256:$src1, VR256:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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[(set VR256:$dst, (v4i64 (OpNode VR256:$src1, VR256:$src2)))]>;
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def rm : PDI<opc, MRMSrcMem, (outs VR256:$dst),
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(ins VR256:$src1, i256mem:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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[(set VR256:$dst, (OpNode VR256:$src1, (memopv4i64 addr:$src2)))]>;
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}
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} // ExeDomain = SSEPackedInt
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// 128-bit Integer Arithmetic
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@ -3475,7 +3434,8 @@ defm VPADDW : PDI_binop_rm<0xFD, "vpaddw", add, v8i16, VR128, memopv2i64,
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i128mem, 1, 0>, VEX_4V;
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defm VPADDD : PDI_binop_rm<0xFE, "vpaddd", add, v4i32, VR128, memopv2i64,
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i128mem, 1, 0>, VEX_4V;
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defm VPADDQ : PDI_binop_rm_v2i64<0xD4, "vpaddq", add, 1, 0>, VEX_4V;
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defm VPADDQ : PDI_binop_rm<0xD4, "vpaddq", add, v2i64, VR128, memopv2i64,
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i128mem, 1, 0>, VEX_4V;
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defm VPMULLW : PDI_binop_rm<0xD5, "vpmullw", mul, v8i16, VR128, memopv2i64,
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i128mem, 1, 0>, VEX_4V;
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defm VPSUBB : PDI_binop_rm<0xF8, "vpsubb", sub, v16i8, VR128, memopv2i64,
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@ -3484,7 +3444,8 @@ defm VPSUBW : PDI_binop_rm<0xF9, "vpsubw", sub, v8i16, VR128, memopv2i64,
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i128mem, 0, 0>, VEX_4V;
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defm VPSUBD : PDI_binop_rm<0xFA, "vpsubd", sub, v4i32, VR128, memopv2i64,
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i128mem, 0, 0>, VEX_4V;
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defm VPSUBQ : PDI_binop_rm_v2i64<0xFB, "vpsubq", sub, 0, 0>, VEX_4V;
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defm VPSUBQ : PDI_binop_rm<0xFB, "vpsubq", sub, v2i64, VR128, memopv2i64,
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i128mem, 0, 0>, VEX_4V;
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// Intrinsic forms
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defm VPSUBSB : PDI_binop_rm_int<0xE8, "vpsubsb" , int_x86_sse2_psubs_b,
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@ -3529,21 +3490,23 @@ defm VPSADBW : PDI_binop_rm_int<0xF6, "vpsadbw", int_x86_sse2_psad_bw,
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let Predicates = [HasAVX2] in {
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defm VPADDBY : PDI_binop_rm<0xFC, "vpaddb", add, v32i8, VR256, memopv4i64,
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i256mem, 1, 0>, VEX_4V;
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i256mem, 1, 0>, VEX_4V;
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defm VPADDWY : PDI_binop_rm<0xFD, "vpaddw", add, v16i16, VR256, memopv4i64,
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i256mem, 1, 0>, VEX_4V;
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i256mem, 1, 0>, VEX_4V;
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defm VPADDDY : PDI_binop_rm<0xFE, "vpaddd", add, v8i32, VR256, memopv4i64,
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i256mem, 1, 0>, VEX_4V;
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defm VPADDQY : PDI_binop_rm_v4i64<0xD4, "vpaddq", add, 1>, VEX_4V;
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i256mem, 1, 0>, VEX_4V;
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defm VPADDQY : PDI_binop_rm<0xD4, "vpaddq", add, v4i64, VR256, memopv4i64,
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i256mem, 1, 0>, VEX_4V;
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defm VPMULLWY : PDI_binop_rm<0xD5, "vpmullw", mul, v16i16, VR256, memopv4i64,
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i256mem, 1, 0>, VEX_4V;
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i256mem, 1, 0>, VEX_4V;
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defm VPSUBBY : PDI_binop_rm<0xF8, "vpsubb", sub, v32i8, VR256, memopv4i64,
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i256mem, 0, 0>, VEX_4V;
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i256mem, 0, 0>, VEX_4V;
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defm VPSUBWY : PDI_binop_rm<0xF9, "vpsubw", sub, v16i16,VR256, memopv4i64,
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i256mem, 0, 0>, VEX_4V;
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i256mem, 0, 0>, VEX_4V;
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defm VPSUBDY : PDI_binop_rm<0xFA, "vpsubd", sub, v8i32, VR256, memopv4i64,
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i256mem, 0, 0>, VEX_4V;
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defm VPSUBQY : PDI_binop_rm_v4i64<0xFB, "vpsubq", sub, 0>, VEX_4V;
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i256mem, 0, 0>, VEX_4V;
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defm VPSUBQY : PDI_binop_rm<0xFB, "vpsubq", sub, v4i64, VR256, memopv4i64,
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i256mem, 0, 0>, VEX_4V;
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// Intrinsic forms
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defm VPSUBSBY : PDI_binop_rm_int<0xE8, "vpsubsb" , int_x86_avx2_psubs_b,
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@ -3593,7 +3556,8 @@ defm PADDW : PDI_binop_rm<0xFD, "paddw", add, v8i16, VR128, memopv2i64,
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i128mem, 1>;
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defm PADDD : PDI_binop_rm<0xFE, "paddd", add, v4i32, VR128, memopv2i64,
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i128mem, 1>;
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defm PADDQ : PDI_binop_rm_v2i64<0xD4, "paddq", add, 1>;
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defm PADDQ : PDI_binop_rm<0xD4, "paddq", add, v2i64, VR128, memopv2i64,
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i128mem, 1>;
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defm PMULLW : PDI_binop_rm<0xD5, "pmullw", mul, v8i16, VR128, memopv2i64,
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i128mem, 1>;
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defm PSUBB : PDI_binop_rm<0xF8, "psubb", sub, v16i8, VR128, memopv2i64,
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@ -3602,7 +3566,8 @@ defm PSUBW : PDI_binop_rm<0xF9, "psubw", sub, v8i16, VR128, memopv2i64,
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i128mem>;
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defm PSUBD : PDI_binop_rm<0xFA, "psubd", sub, v4i32, VR128, memopv2i64,
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i128mem>;
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defm PSUBQ : PDI_binop_rm_v2i64<0xFB, "psubq", sub>;
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defm PSUBQ : PDI_binop_rm<0xFB, "psubq", sub, v2i64, VR128, memopv2i64,
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i128mem>;
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// Intrinsic forms
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defm PSUBSB : PDI_binop_rm_int<0xE8, "psubsb" , int_x86_sse2_psubs_b,
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@ -3678,9 +3643,12 @@ defm VPSRAD : PDI_binop_rmi_int<0xE2, 0x72, MRM4r, "vpsrad",
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int_x86_sse2_psra_d, int_x86_sse2_psrai_d,
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VR128, 0>, VEX_4V;
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defm VPAND : PDI_binop_rm_v2i64<0xDB, "vpand", and, 1, 0>, VEX_4V;
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defm VPOR : PDI_binop_rm_v2i64<0xEB, "vpor" , or, 1, 0>, VEX_4V;
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defm VPXOR : PDI_binop_rm_v2i64<0xEF, "vpxor", xor, 1, 0>, VEX_4V;
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defm VPAND : PDI_binop_rm<0xDB, "vpand", and, v2i64, VR128, memopv2i64,
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i128mem, 1, 0>, VEX_4V;
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defm VPOR : PDI_binop_rm<0xEB, "vpor" , or, v2i64, VR128, memopv2i64,
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i128mem, 1, 0>, VEX_4V;
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defm VPXOR : PDI_binop_rm<0xEF, "vpxor", xor, v2i64, VR128, memopv2i64,
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i128mem, 1, 0>, VEX_4V;
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let ExeDomain = SSEPackedInt in {
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let neverHasSideEffects = 1 in {
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@ -3737,9 +3705,12 @@ defm VPSRADY : PDI_binop_rmi_int<0xE2, 0x72, MRM4r, "vpsrad",
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int_x86_avx2_psra_d, int_x86_avx2_psrai_d,
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VR256, 0>, VEX_4V;
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defm VPANDY : PDI_binop_rm_v4i64<0xDB, "vpand", and, 1>, VEX_4V;
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defm VPORY : PDI_binop_rm_v4i64<0xEB, "vpor" , or, 1>, VEX_4V;
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defm VPXORY : PDI_binop_rm_v4i64<0xEF, "vpxor", xor, 1>, VEX_4V;
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defm VPANDY : PDI_binop_rm<0xDB, "vpand", and, v4i64, VR256, memopv4i64,
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i256mem, 1, 0>, VEX_4V;
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defm VPORY : PDI_binop_rm<0xEB, "vpor", or, v4i64, VR256, memopv4i64,
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i256mem, 1, 0>, VEX_4V;
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defm VPXORY : PDI_binop_rm<0xEF, "vpxor", xor, v4i64, VR256, memopv4i64,
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i256mem, 1, 0>, VEX_4V;
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let ExeDomain = SSEPackedInt in {
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let neverHasSideEffects = 1 in {
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@ -3796,9 +3767,12 @@ defm PSRAD : PDI_binop_rmi_int<0xE2, 0x72, MRM4r, "psrad",
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int_x86_sse2_psra_d, int_x86_sse2_psrai_d,
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VR128>;
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defm PAND : PDI_binop_rm_v2i64<0xDB, "pand", and, 1>;
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defm POR : PDI_binop_rm_v2i64<0xEB, "por" , or, 1>;
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defm PXOR : PDI_binop_rm_v2i64<0xEF, "pxor", xor, 1>;
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defm PAND : PDI_binop_rm<0xDB, "pand", and, v2i64, VR128, memopv2i64,
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i128mem, 1>;
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defm POR : PDI_binop_rm<0xEB, "por" , or, v2i64, VR128, memopv2i64,
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i128mem, 1>;
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defm PXOR : PDI_binop_rm<0xEF, "pxor", xor, v2i64, VR128, memopv2i64,
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i128mem, 1>;
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let ExeDomain = SSEPackedInt in {
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let neverHasSideEffects = 1 in {
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@ -7741,62 +7715,38 @@ defm VPMASKMOVQ : avx2_pmovmask<"vpmaskmovq",
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//===----------------------------------------------------------------------===//
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// Variable Bit Shifts
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//
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multiclass avx2_var_shift_i32<bits<8> opc, string OpcodeStr, SDNode OpNode> {
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multiclass avx2_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
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ValueType vt128, ValueType vt256> {
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def rr : AVX28I<opc, MRMSrcReg, (outs VR128:$dst),
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(ins VR128:$src1, VR128:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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[(set VR128:$dst,
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(v4i32 (OpNode VR128:$src1, (v4i32 VR128:$src2))))]>,
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(vt128 (OpNode VR128:$src1, (vt128 VR128:$src2))))]>,
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VEX_4V;
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def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst),
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(ins VR128:$src1, i128mem:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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[(set VR128:$dst,
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(v4i32 (OpNode VR128:$src1,
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(bc_v4i32 (memopv2i64 addr:$src2)))))]>, VEX_4V;
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def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst),
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(ins VR256:$src1, VR256:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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[(set VR256:$dst,
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(v8i32 (OpNode VR256:$src1, (v8i32 VR256:$src2))))]>,
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VEX_4V;
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def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst),
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(ins VR256:$src1, i256mem:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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[(set VR256:$dst,
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(v8i32 (OpNode VR256:$src1,
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(bc_v8i32 (memopv4i64 addr:$src2)))))]>, VEX_4V;
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}
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multiclass avx2_var_shift_i64<bits<8> opc, string OpcodeStr, SDNode OpNode> {
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def rr : AVX28I<opc, MRMSrcReg, (outs VR128:$dst),
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(ins VR128:$src1, VR128:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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[(set VR128:$dst,
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(v2i64 (OpNode VR128:$src1, (v2i64 VR128:$src2))))]>,
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VEX_4V;
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def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst),
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(ins VR128:$src1, i128mem:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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[(set VR128:$dst,
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(v2i64 (OpNode VR128:$src1, (memopv2i64 addr:$src2))))]>,
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(vt128 (OpNode VR128:$src1,
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(vt128 (bitconvert (memopv2i64 addr:$src2))))))]>,
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VEX_4V;
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def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst),
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(ins VR256:$src1, VR256:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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[(set VR256:$dst,
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(v4i64 (OpNode VR256:$src1, (v4i64 VR256:$src2))))]>,
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(vt256 (OpNode VR256:$src1, (vt256 VR256:$src2))))]>,
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VEX_4V;
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def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst),
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(ins VR256:$src1, i256mem:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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[(set VR256:$dst,
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(v4i64 (OpNode VR256:$src1, (memopv4i64 addr:$src2))))]>,
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(vt256 (OpNode VR256:$src1,
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(vt256 (bitconvert (memopv4i64 addr:$src2))))))]>,
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VEX_4V;
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}
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defm VPSLLVD : avx2_var_shift_i32<0x47, "vpsllvd", shl>;
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defm VPSLLVQ : avx2_var_shift_i64<0x47, "vpsllvq", shl>, VEX_W;
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defm VPSRLVD : avx2_var_shift_i32<0x45, "vpsrlvd", srl>;
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defm VPSRLVQ : avx2_var_shift_i64<0x45, "vpsrlvq", srl>, VEX_W;
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defm VPSRAVD : avx2_var_shift_i32<0x46, "vpsravd", sra>;
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defm VPSLLVD : avx2_var_shift<0x47, "vpsllvd", shl, v4i32, v8i32>;
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defm VPSLLVQ : avx2_var_shift<0x47, "vpsllvq", shl, v2i64, v4i64>, VEX_W;
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defm VPSRLVD : avx2_var_shift<0x45, "vpsrlvd", srl, v4i32, v8i32>;
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defm VPSRLVQ : avx2_var_shift<0x45, "vpsrlvq", srl, v2i64, v4i64>, VEX_W;
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defm VPSRAVD : avx2_var_shift<0x46, "vpsravd", sra, v4i32, v8i32>;
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