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Make register scavenging happy by not using a reg (CR0) that isn't defined

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47045 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Nate Begeman 2008-02-13 02:58:33 +00:00
parent d2b8d7bc51
commit ba8d51c1d7
1 changed files with 1 additions and 1 deletions
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lib/Target/PowerPC/PPCInstrInfo.td
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@ -293,7 +293,7 @@ def memrix : Operand<iPTR> { // memri where the imm is shifted 2 bits.
// PowerPC Predicate operand. 20 = (0<<5)|20 = always, CR0 is a dummy reg
// that doesn't matter.
def pred : PredicateOperand<OtherVT, (ops imm, CRRC),
(ops (i32 20), CR0)> {
(ops (i32 20), (i32 zero_reg))> {
let PrintMethod = "printPredicateOperand";
}