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fold c1 << (x + c2) into (c1 << c2) << x. fix a warning.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26005 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Nate Begeman 2006-02-05 08:07:24 +00:00
parent 176f0416d1
commit bab9239d05
1 changed files with 7 additions and 1 deletions
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8
lib/CodeGen/SelectionDAG/DAGCombiner.cpp
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@ -838,7 +838,7 @@ SDOperand DAGCombiner::visitUREM(SDNode *N) {
if (N1.getOpcode() == ISD::SHL) {
if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
if (isPowerOf2_64(SHC->getValue())) {
SDOperand Add = DAG.getNode(ISD::ADD, VT, N1, DAG.getConstant(-1, VT));
SDOperand Add = DAG.getNode(ISD::ADD, VT, N1,DAG.getConstant(~0ULL,VT));
WorkList.push_back(Add.Val);
return DAG.getNode(ISD::AND, VT, N0, Add);
}
@ -1288,6 +1288,12 @@ SDOperand DAGCombiner::visitSHL(SDNode *N) {
// fold (shl 0, x) -> 0
if (N0C && N0C->isNullValue())
return N0;
// fold (shl c1, (add x, c2)) -> (shl c1 << c2, x)
if (N0C && N1.getOpcode() == ISD::ADD &&
N1.getOperand(1).getOpcode() == ISD::Constant) {
SDOperand LHS = DAG.getNode(ISD::SHL, VT, N0, N1.getOperand(1));
return DAG.getNode(ISD::SHL, VT, LHS, N1.getOperand(0));
}
// fold (shl x, c >= size(x)) -> undef
if (N1C && N1C->getValue() >= OpSizeInBits)
return DAG.getNode(ISD::UNDEF, VT);