From bac932e9c3c4305a3c73598f3d0dc55de53d4c68 Mon Sep 17 00:00:00 2001 From: Mihai Popa Date: Mon, 20 May 2013 14:42:43 +0000 Subject: [PATCH] Q registers are encoded in fields of the same length as D registers. As Q registers are half as many, the ARM reference manual mandates the least significant bit to be zeroed out. Failure to do so should result in an undefined instruction. With this change test/MC/Disassembler/ARM/invalid-VQADD-arm.txt is passing (removed XFAIL). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182279 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/Disassembler/ARMDisassembler.cpp | 2 +- test/MC/Disassembler/ARM/invalid-VQADD-arm.txt | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp index c562cf7a717..aa59c98296c 100644 --- a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp +++ b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp @@ -1048,7 +1048,7 @@ static const uint16_t QPRDecoderTable[] = { static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) { - if (RegNo > 31) + if (RegNo > 31 || (RegNo & 1) != 0) return MCDisassembler::Fail; RegNo >>= 1; diff --git a/test/MC/Disassembler/ARM/invalid-VQADD-arm.txt b/test/MC/Disassembler/ARM/invalid-VQADD-arm.txt index f961c64f7d9..e8e5d6fa21c 100644 --- a/test/MC/Disassembler/ARM/invalid-VQADD-arm.txt +++ b/test/MC/Disassembler/ARM/invalid-VQADD-arm.txt @@ -1,5 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=armv7-unknown-unknwon -mcpu=cortex-a8 2>&1 | grep "invalid instruction encoding" -# XFAIL: * +# RUN: llvm-mc --disassemble %s -triple=armv7-unknown-unknwon -mcpu=cortex-a8 2>&1 | FileCheck %s # Opcode=1225 Name=VQADDsv16i8 Format=ARM_FORMAT_N3Reg(37) # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 @@ -9,3 +8,4 @@ # # Qm -> bit[0] == 0, otherwise UNDEFINED 0xdb 0xe0 0x40 0xf2 +# CHECK: invalid instruction encoding