6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-11-02 22:04:55 +00:00
Code Issues Projects Releases Wiki Activity

Remove unused member variable.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103936 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Zhongxing Xu 2010-05-17 09:47:55 +00:00
parent 0c9e4f5f3f
commit bae5210321
2 changed files with 0 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
include/llvm/CodeGen/ScheduleDAG.h
View File

@ -34,7 +34,6 @@ namespace llvm {
class SDNode;
class TargetInstrInfo;
class TargetInstrDesc;
class TargetLowering;
class TargetMachine;
class TargetRegisterClass;
template<class Graph> class GraphWriter;
@ -456,7 +455,6 @@ namespace llvm {
const TargetMachine &TM; // Target processor
const TargetInstrInfo *TII; // Target instruction information
const TargetRegisterInfo *TRI; // Target processor register info
const TargetLowering *TLI; // Target lowering info
MachineFunction &MF; // Machine function
MachineRegisterInfo &MRI; // Virtual/real register map
std::vector<SUnit*> Sequence; // The schedule. Null SUnit*'s

1
lib/CodeGen/ScheduleDAG.cpp
View File

@ -27,7 +27,6 @@ ScheduleDAG::ScheduleDAG(MachineFunction &mf)
: TM(mf.getTarget()),
TII(TM.getInstrInfo()),
TRI(TM.getRegisterInfo()),
TLI(TM.getTargetLowering()),
MF(mf), MRI(mf.getRegInfo()),
EntrySU(), ExitSU() {
}