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Fixed a bug when trying to optimize a extract vector element of a
bit convert that changes the number of elements of a shuffle. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60829 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -4874,7 +4874,8 @@ SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) {
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MVT LVT = EVT;
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if (InVec.getOpcode() == ISD::BIT_CONVERT) {
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MVT BCVT = InVec.getOperand(0).getValueType();
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if (!BCVT.isVector() || EVT.bitsGT(BCVT.getVectorElementType()))
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if (!BCVT.isVector() || EVT.bitsGT(BCVT.getVectorElementType()) ||
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VT.getVectorNumElements() != BCVT.getVectorNumElements())
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return SDValue();
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InVec = InVec.getOperand(0);
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EVT = BCVT.getVectorElementType();
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13
test/CodeGen/X86/extractelement-shuffle.ll
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13
test/CodeGen/X86/extractelement-shuffle.ll
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@ -0,0 +1,13 @@
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; RUN: llvm-as < %s | llc
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; Examples that exhibits a bug in DAGCombine. The case is triggered by the
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; following program. The bug is DAGCombine assumes that the bit convert
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; preserves the number of elements so the optimization code tries to read
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; through the 3rd mask element, which doesn't exist.
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define i32 @update(<2 x i64> %val1, <2 x i64> %val2) nounwind readnone {
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entry:
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%shuf = shufflevector <2 x i64> %val1, <2 x i64> %val2, <2 x i32> <i32 0, i32 3>;
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%bit = bitcast <2 x i64> %shuf to <4 x i32>;
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%res = extractelement <4 x i32> %bit, i32 3;
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ret i32 %res;
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}
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