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[mips][microMIPS] Implement SDBBP and RDHWR instructions.

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Differential Revision: http://reviews.llvm.org/D5240


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222347 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jozef Kolek 2014-11-19 11:25:50 +00:00
parent 0e2f3ce8a0
commit baf97d8987
6 changed files with 61 additions and 4 deletions
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24
lib/Target/Mips/MicroMipsInstrFormats.td
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@ -765,3 +765,27 @@ class COP0_TLB_FM_MM<bits<10> op> : MMArch {
let Inst{15-6} = op;
let Inst{5-0} = 0x3c;
}
class SDBBP_FM_MM : MMArch {
bits<10> code_;
bits<32> Inst;
let Inst{31-26} = 0x0;
let Inst{25-16} = code_;
let Inst{15-6} = 0x36d;
let Inst{5-0} = 0x3c;
}
class RDHWR_FM_MM : MMArch {
bits<5> rt;
bits<5> rd;
bits<32> Inst;
let Inst{31-26} = 0x0;
let Inst{25-21} = rt;
let Inst{20-16} = rd;
let Inst{15-6} = 0x1ac;
let Inst{5-0} = 0x3c;
}

3
lib/Target/Mips/MicroMipsInstrInfo.td
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@ -508,6 +508,9 @@ let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in {
def TLBR_MM : MMRel, TLB<"tlbr">, COP0_TLB_FM_MM<0x4d>;
def TLBWI_MM : MMRel, TLB<"tlbwi">, COP0_TLB_FM_MM<0x8d>;
def TLBWR_MM : MMRel, TLB<"tlbwr">, COP0_TLB_FM_MM<0xcd>;
def SDBBP_MM : MMRel, SYS_FT<"sdbbp">, SDBBP_FM_MM;
def RDHWR_MM : MMRel, ReadHardware<GPR32Opnd, HWRegsOpnd>, RDHWR_FM_MM;
}
let Predicates = [InMicroMips] in {

2
lib/Target/Mips/MipsInstrFormats.td
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@ -440,7 +440,7 @@ class EXT_FM<bits<6> funct> : StdArch {
let Inst{5-0} = funct;
}
class RDHWR_FM {
class RDHWR_FM : StdArch {
bits<5> rt;
bits<5> rd;

6
lib/Target/Mips/MipsInstrInfo.td
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@ -970,7 +970,7 @@ class SubwordSwap<string opstr, RegisterOperand RO>:
// Read Hardware
class ReadHardware<RegisterOperand CPURegOperand, RegisterOperand RO> :
InstSE<(outs CPURegOperand:$rt), (ins RO:$rd), "rdhwr\t$rt, $rd", [],
II_RDHWR, FrmR>;
II_RDHWR, FrmR, "rdhwr">;
// Ext and Ins
class ExtBase<string opstr, RegisterOperand RO, Operand PosOpnd,
@ -1232,7 +1232,7 @@ def TNEI : MMRel, TEQI_FT<"tnei", GPR32Opnd>, TEQI_FM<0xe>,
def BREAK : MMRel, BRK_FT<"break">, BRK_FM<0xd>;
def SYSCALL : MMRel, SYS_FT<"syscall">, SYS_FM<0xc>;
def TRAP : TrapBase<BREAK>;
def SDBBP : SYS_FT<"sdbbp">, SDBBP_FM, ISA_MIPS32_NOT_32R6_64R6;
def SDBBP : MMRel, SYS_FT<"sdbbp">, SDBBP_FM, ISA_MIPS32_NOT_32R6_64R6;
def ERET : MMRel, ER_FT<"eret">, ER_FM<0x18>, INSN_MIPS3_32;
def DERET : MMRel, ER_FT<"deret">, ER_FM<0x1f>, ISA_MIPS32;
@ -1427,7 +1427,7 @@ def PseudoSDIV : MultDivPseudo<SDIV, ACC64, GPR32Opnd, MipsDivRem, II_DIV,
def PseudoUDIV : MultDivPseudo<UDIV, ACC64, GPR32Opnd, MipsDivRemU, II_DIVU,
0, 1, 1>, ISA_MIPS1_NOT_32R6_64R6;
def RDHWR : ReadHardware<GPR32Opnd, HWRegsOpnd>, RDHWR_FM;
def RDHWR : MMRel, ReadHardware<GPR32Opnd, HWRegsOpnd>, RDHWR_FM;
def EXT : MMRel, ExtBase<"ext", GPR32Opnd, uimm5, MipsExt>, EXT_FM<0>;
def INS : MMRel, InsBase<"ins", GPR32Opnd, uimm5, MipsIns>, EXT_FM<4>;

15
test/CodeGen/Mips/micromips-rdhwr-directives.ll Normal file
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@ -0,0 +1,15 @@
; RUN: llc -march=mipsel -mcpu=mips32 -relocation-model=static < %s \
; RUN: -mattr=+micromips | FileCheck %s
@a = external thread_local global i32
define i32 @foo() nounwind readonly {
entry:
; CHECK: .set push
; CHECK: .set mips32r2
; CHECK: rdhwr
; CHECK: .set pop
%0 = load i32* @a, align 4
ret i32 %0
}

15
test/MC/Mips/micromips-control-instructions.s
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@ -9,6 +9,12 @@
#------------------------------------------------------------------------------
# Little endian
#------------------------------------------------------------------------------
# CHECK-EL: sdbbp # encoding: [0x00,0x00,0x7c,0xdb]
# CHECK-EL: sdbbp 34 # encoding: [0x22,0x00,0x7c,0xdb]
# CHECK-EL: .set push
# CHECK-EL: .set mips32r2
# CHECK-EL: rdhwr $5, $29
# CHECK-EL: .set pop # encoding: [0xbd,0x00,0x3c,0x6b]
# CHECK-EL: break # encoding: [0x00,0x00,0x07,0x00]
# CHECK-EL: break 7 # encoding: [0x07,0x00,0x07,0x00]
# CHECK-EL: break 7, 5 # encoding: [0x07,0x00,0x47,0x01]
@ -31,6 +37,12 @@
#------------------------------------------------------------------------------
# Big endian
#------------------------------------------------------------------------------
# CHECK-EB: sdbbp # encoding: [0x00,0x00,0xdb,0x7c]
# CHECK-EB: sdbbp 34 # encoding: [0x00,0x22,0xdb,0x7c]
# CHECK-EB: .set push
# CHECK-EB: .set mips32r2
# CHECK-EB: rdhwr $5, $29
# CHECK-EB: .set pop # encoding: [0x00,0xbd,0x6b,0x3c]
# CHECK-EB: break # encoding: [0x00,0x00,0x00,0x07]
# CHECK-EB: break 7 # encoding: [0x00,0x07,0x00,0x07]
# CHECK-EB: break 7, 5 # encoding: [0x00,0x07,0x01,0x47]
@ -51,6 +63,9 @@
# CHECK-EB: tlbwi # encoding: [0x00,0x00,0x23,0x7c]
# CHECK-EB: tlbwr # encoding: [0x00,0x00,0x33,0x7c]
sdbbp
sdbbp 34
rdhwr $5, $29
break
break 7
break 7,5