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More APInt-ification.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47868 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1518,17 +1518,13 @@ unsigned SelectionDAG::ComputeNumSignBits(SDOperand Op, unsigned Depth) const{
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return VTBits-Tmp;
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case ISD::Constant: {
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uint64_t Val = cast<ConstantSDNode>(Op)->getValue();
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// If negative, invert the bits, then look at it.
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if (Val & MVT::getIntVTSignBit(VT))
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Val = ~Val;
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const APInt &Val = cast<ConstantSDNode>(Op)->getAPIntValue();
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// If negative, return # leading ones.
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if (Val.isNegative())
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return Val.countLeadingOnes();
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// Shift the bits so they are the leading bits in the int64_t.
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Val <<= 64-VTBits;
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// Return # leading zeros. We use 'min' here in case Val was zero before
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// shifting. We don't want to return '64' as for an i32 "0".
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return std::min(VTBits, CountLeadingZeros_64(Val));
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// Return # leading zeros.
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return Val.countLeadingZeros();
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}
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case ISD::SIGN_EXTEND:
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