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Minimize the slot indexes spanned by register ranges created when splitting.
When an interfering live range ends at a dead slot index between two instructions, make sure that the inserted copy instruction gets a slot index after the dead ones. This makes it possible to avoid the interference. Ideally, there shouldn't be interference ending at a deleted instruction, but physical register coalescing can sometimes do that to sub-registers. This fixes PR9823. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130687 91177308-0d34-0410-b5e6-96231b3b80d8
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@@ -140,11 +140,13 @@ SlotIndex LiveRangeEdit::rematerializeAt(MachineBasicBlock &MBB,
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const Remat &RM,
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const Remat &RM,
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LiveIntervals &lis,
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LiveIntervals &lis,
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const TargetInstrInfo &tii,
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const TargetInstrInfo &tii,
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const TargetRegisterInfo &tri) {
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const TargetRegisterInfo &tri,
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bool Late) {
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assert(RM.OrigMI && "Invalid remat");
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assert(RM.OrigMI && "Invalid remat");
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tii.reMaterialize(MBB, MI, DestReg, 0, RM.OrigMI, tri);
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tii.reMaterialize(MBB, MI, DestReg, 0, RM.OrigMI, tri);
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rematted_.insert(RM.ParentVNI);
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rematted_.insert(RM.ParentVNI);
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return lis.InsertMachineInstrInMaps(--MI).getDefIndex();
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return lis.getSlotIndexes()->insertMachineInstrInMaps(--MI, Late)
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.getDefIndex();
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}
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}
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void LiveRangeEdit::eraseVirtReg(unsigned Reg, LiveIntervals &LIS) {
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void LiveRangeEdit::eraseVirtReg(unsigned Reg, LiveIntervals &LIS) {
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@@ -165,7 +165,8 @@ public:
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const Remat &RM,
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const Remat &RM,
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LiveIntervals&,
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LiveIntervals&,
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const TargetInstrInfo&,
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const TargetInstrInfo&,
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const TargetRegisterInfo&);
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const TargetRegisterInfo&,
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bool Late = false);
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/// markRematerialized - explicitly mark a value as rematerialized after doing
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/// markRematerialized - explicitly mark a value as rematerialized after doing
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/// it manually.
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/// it manually.
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@@ -579,15 +579,20 @@ VNInfo *SplitEditor::defFromParent(unsigned RegIdx,
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SlotIndex Def;
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SlotIndex Def;
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LiveInterval *LI = Edit->get(RegIdx);
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LiveInterval *LI = Edit->get(RegIdx);
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// We may be trying to avoid interference that ends at a deleted instruction,
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// so always begin RegIdx 0 early and all others late.
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bool Late = RegIdx != 0;
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// Attempt cheap-as-a-copy rematerialization.
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// Attempt cheap-as-a-copy rematerialization.
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LiveRangeEdit::Remat RM(ParentVNI);
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LiveRangeEdit::Remat RM(ParentVNI);
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if (Edit->canRematerializeAt(RM, UseIdx, true, LIS)) {
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if (Edit->canRematerializeAt(RM, UseIdx, true, LIS)) {
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Def = Edit->rematerializeAt(MBB, I, LI->reg, RM, LIS, TII, TRI);
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Def = Edit->rematerializeAt(MBB, I, LI->reg, RM, LIS, TII, TRI, Late);
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} else {
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} else {
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// Can't remat, just insert a copy from parent.
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// Can't remat, just insert a copy from parent.
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CopyMI = BuildMI(MBB, I, DebugLoc(), TII.get(TargetOpcode::COPY), LI->reg)
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CopyMI = BuildMI(MBB, I, DebugLoc(), TII.get(TargetOpcode::COPY), LI->reg)
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.addReg(Edit->getReg());
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.addReg(Edit->getReg());
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Def = LIS.InsertMachineInstrInMaps(CopyMI).getDefIndex();
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Def = LIS.getSlotIndexes()->insertMachineInstrInMaps(CopyMI, Late)
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.getDefIndex();
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}
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}
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// Define the value in Reg.
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// Define the value in Reg.
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