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ARM: Tweak tADDrSP definition for consistent operand order.
Make the operand order of the instruction match that of the asm syntax. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155747 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -363,8 +363,8 @@ def : tInstAlias<"sub${p} sp, sp, $imm",
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(tSUBspi SP, t_imm0_508s4:$imm, pred:$p)>;
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// ADD <Rm>, sp
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def tADDrSP : T1pIt<(outs GPR:$Rdn), (ins GPR:$Rn, GPRsp:$sp), IIC_iALUr,
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"add", "\t$Rdn, $sp, $Rn", []>,
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def tADDrSP : T1pIt<(outs GPR:$Rdn), (ins GPRsp:$sp, GPR:$Rn), IIC_iALUr,
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"add", "\t$Rdn, $sp, $Rn", []>,
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T1Special<{0,0,?,?}> {
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// A8.6.9 Encoding T1
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bits<4> Rdn;
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@ -3296,9 +3296,9 @@ static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn,
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if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
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return MCDisassembler::Fail;
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Inst.addOperand(MCOperand::CreateReg(ARM::SP));
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if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
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return MCDisassembler::Fail;
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Inst.addOperand(MCOperand::CreateReg(ARM::SP));
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} else if (Inst.getOpcode() == ARM::tADDspr) {
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unsigned Rm = fieldFromInstruction16(Insn, 3, 4);
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