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Emit libcalls for SDIV, this requires some call infrastructure
that needs to be shared a bit more widely around. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113886 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -24,6 +24,7 @@
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#include "llvm/GlobalVariable.h"
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#include "llvm/Instructions.h"
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#include "llvm/IntrinsicInst.h"
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#include "llvm/Module.h"
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#include "llvm/CodeGen/Analysis.h"
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#include "llvm/CodeGen/FastISel.h"
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#include "llvm/CodeGen/FunctionLoweringInfo.h"
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@ -121,6 +122,7 @@ class ARMFastISel : public FastISel {
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virtual bool ARMSelectBinaryOp(const Instruction *I, unsigned ISDOpcode);
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virtual bool ARMSelectSIToFP(const Instruction *I);
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virtual bool ARMSelectFPToSI(const Instruction *I);
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virtual bool ARMSelectSDiv(const Instruction *I);
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// Utility routines.
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private:
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@ -139,6 +141,7 @@ class ARMFastISel : public FastISel {
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// Call handling routines.
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private:
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CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool Return);
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bool ARMEmitLibcall(const Instruction *I, Function *F);
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// OptionalDef handling routines.
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private:
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@ -931,6 +934,155 @@ CCAssignFn *ARMFastISel::CCAssignFnForCall(CallingConv::ID CC, bool Return) {
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}
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}
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// A quick function that will emit a call for a named libcall in F with the
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// vector of passed arguments for the Instruction in I. We can assume that we
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// can emit a call for any libcall we can produce. This is an abridged version
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// of the full call infrastructure since we won't need to worry about things
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// like computed function pointers or strange arguments at call sites.
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// TODO: Try to unify this and the normal call bits for ARM, then try to unify
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// with X86.
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bool ARMFastISel::ARMEmitLibcall(const Instruction *I, Function *F) {
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CallingConv::ID CC = F->getCallingConv();
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// Handle *simple* calls for now.
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const Type *RetTy = F->getReturnType();
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EVT RetVT;
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if (RetTy->isVoidTy())
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RetVT = MVT::isVoid;
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else if (!isTypeLegal(RetTy, RetVT))
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return false;
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assert(!F->isVarArg() && "Vararg libcall?!");
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// Abridged from the X86 FastISel call selection mechanism
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SmallVector<Value*, 8> Args;
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SmallVector<unsigned, 8> ArgRegs;
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SmallVector<EVT, 8> ArgVTs;
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SmallVector<ISD::ArgFlagsTy, 8> ArgFlags;
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Args.reserve(I->getNumOperands());
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ArgRegs.reserve(I->getNumOperands());
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ArgVTs.reserve(I->getNumOperands());
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ArgFlags.reserve(I->getNumOperands());
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for (unsigned i = 0; i < Args.size(); ++i) {
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Value *Op = I->getOperand(i);
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unsigned Arg = getRegForValue(Op);
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if (Arg == 0) return false;
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const Type *ArgTy = Op->getType();
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EVT ArgVT;
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if (!isTypeLegal(ArgTy, ArgVT)) return false;
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ISD::ArgFlagsTy Flags;
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unsigned OriginalAlignment = TD.getABITypeAlignment(ArgTy);
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Flags.setOrigAlign(OriginalAlignment);
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Args.push_back(Op);
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ArgRegs.push_back(Arg);
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ArgVTs.push_back(ArgVT);
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ArgFlags.push_back(Flags);
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}
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SmallVector<CCValAssign, 16> ArgLocs;
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CCState CCInfo(CC, false, TM, ArgLocs, F->getContext());
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CCInfo.AnalyzeCallOperands(ArgVTs, ArgFlags, CCAssignFnForCall(CC, false));
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// Process the args.
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SmallVector<unsigned, 4> RegArgs;
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for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
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CCValAssign &VA = ArgLocs[i];
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unsigned Arg = ArgRegs[VA.getValNo()];
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EVT ArgVT = ArgVTs[VA.getValNo()];
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// Should we ever have to promote?
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switch (VA.getLocInfo()) {
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case CCValAssign::Full: break;
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default:
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assert(false && "Handle arg promotion for libcalls?");
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return false;
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}
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// Now copy/store arg to correct locations.
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if (VA.isRegLoc()) {
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
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VA.getLocReg()).addReg(Arg);
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RegArgs.push_back(VA.getLocReg());
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} else {
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// Need to store
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return false;
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}
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}
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// Issue the call, BLr9 for darwin, BL otherwise.
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MachineInstrBuilder MIB;
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unsigned CallOpc = Subtarget->isTargetDarwin() ? ARM::BLr9 : ARM::BL;
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MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CallOpc))
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.addGlobalAddress(F, 0, 0);
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// Add implicit physical register uses to the call.
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for (unsigned i = 0, e = RegArgs.size(); i != e; ++i)
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MIB.addReg(RegArgs[i]);
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// Now the return value.
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SmallVector<unsigned, 4> UsedRegs;
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if (RetVT.getSimpleVT().SimpleTy != MVT::isVoid) {
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SmallVector<CCValAssign, 16> RVLocs;
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CCState CCInfo(CC, false, TM, RVLocs, F->getContext());
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CCInfo.AnalyzeCallResult(RetVT, CCAssignFnForCall(CC, true));
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// Copy all of the result registers out of their specified physreg.
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assert(RVLocs.size() == 1 && "Can't handle multi-value calls!");
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EVT CopyVT = RVLocs[0].getValVT();
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TargetRegisterClass* DstRC = TLI.getRegClassFor(CopyVT);
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unsigned ResultReg = createResultReg(DstRC);
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
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ResultReg).addReg(RVLocs[0].getLocReg());
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UsedRegs.push_back(RVLocs[0].getLocReg());
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// Finally update the result.
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UpdateValueMap(I, ResultReg);
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}
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// Set all unused physreg defs as dead.
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static_cast<MachineInstr *>(MIB)->setPhysRegsDeadExcept(UsedRegs, TRI);
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return true;
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}
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bool ARMFastISel::ARMSelectSDiv(const Instruction *I) {
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EVT VT;
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const Type *Ty = I->getType();
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if (!isTypeLegal(Ty, VT))
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return false;
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// If we have integer div support we should have gotten already, emit a
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// libcall.
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RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
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if (VT == MVT::i16)
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LC = RTLIB::SDIV_I16;
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else if (VT == MVT::i32)
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LC = RTLIB::SDIV_I32;
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else if (VT == MVT::i64)
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LC = RTLIB::SDIV_I64;
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else if (VT == MVT::i128)
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LC = RTLIB::SDIV_I128;
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assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!");
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// Binary operand with all the same type.
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std::vector<const Type*> ArgTys;
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ArgTys.push_back(Ty);
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ArgTys.push_back(Ty);
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const FunctionType *FTy = FunctionType::get(Ty, ArgTys, false);
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Function *F = Function::Create(FTy, GlobalValue::ExternalLinkage,
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TLI.getLibcallName(LC));
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if (Subtarget->isAAPCS_ABI())
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F->setCallingConv(CallingConv::ARM_AAPCS);
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else
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F->setCallingConv(I->getParent()->getParent()->getCallingConv());
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return ARMEmitLibcall(I, F);
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}
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// TODO: SoftFP support.
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bool ARMFastISel::TargetSelectInstruction(const Instruction *I) {
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// No Thumb-1 for now.
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@ -960,6 +1112,8 @@ bool ARMFastISel::TargetSelectInstruction(const Instruction *I) {
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return ARMSelectBinaryOp(I, ISD::FSUB);
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case Instruction::FMul:
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return ARMSelectBinaryOp(I, ISD::FMUL);
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case Instruction::SDiv:
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return ARMSelectSDiv(I);
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default: break;
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}
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return false;
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