6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-08-12 16:29:31 +00:00
Code Issues Projects Releases Wiki Activity

Simplify FastISel's constructor argument list, make the FastISel

Browse Source 
class hold a MachineRegisterInfo member, and make the
MachineBasicBlock be passed in to SelectInstructions rather
than the FastISel constructor.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55076 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Dan Gohman 2008-08-20 21:05:57 +00:00
parent 2385852b5b
commit bb466331e7
8 changed files with 33 additions and 40 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

13
include/llvm/CodeGen/FastISel.h
View File

@ -22,6 +22,7 @@ namespace llvm {
class MachineBasicBlock;
class MachineFunction;
class MachineRegisterInfo;
class TargetInstrInfo;
class TargetRegisterClass;
@ -30,8 +31,9 @@ class TargetRegisterClass;
/// lowering, but runs quickly.
class FastISel {
MachineBasicBlock *MBB;
MachineFunction *MF;
const TargetInstrInfo *TII;
MachineFunction &MF;
MachineRegisterInfo &MRI;
const TargetInstrInfo &TII;
public:
/// SelectInstructions - Do "fast" instruction selection over the
@ -41,14 +43,13 @@ public:
/// register numbers.
BasicBlock::iterator
SelectInstructions(BasicBlock::iterator Begin, BasicBlock::iterator End,
DenseMap<const Value*, unsigned> &ValueMap);
DenseMap<const Value*, unsigned> &ValueMap,
MachineBasicBlock *mbb);
virtual ~FastISel();
protected:
FastISel(MachineBasicBlock *mbb, MachineFunction *mf,
const TargetInstrInfo *tii)
: MBB(mbb), MF(mf), TII(tii) {}
explicit FastISel(MachineFunction &mf);
/// FastEmit_r - This method is called by target-independent code
/// to request that an instruction with the given type and opcode

5
include/llvm/Target/TargetLowering.h
View File

@ -42,7 +42,6 @@ namespace llvm {
class SDValue;
class SelectionDAG;
class TargetData;
class TargetInstrInfo;
class TargetMachine;
class TargetRegisterClass;
class TargetSubtarget;
@ -1116,9 +1115,7 @@ public:
/// createFastISel - This method returns a target specific FastISel object,
/// or null if the target does not support "fast" ISel.
virtual FastISel *createFastISel(MachineBasicBlock *,
MachineFunction *,
const TargetInstrInfo *) { return 0; }
virtual FastISel *createFastISel(MachineFunction &) { return 0; }
//===--------------------------------------------------------------------===//
// Inline Asm Support hooks

26
lib/CodeGen/SelectionDAG/FastISel.cpp
View File

@ -16,6 +16,7 @@
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetMachine.h"
using namespace llvm;
/// SelectBinaryOp - Select and emit code for a binary operator instruction,
@ -54,7 +55,9 @@ bool FastISel::SelectGetElementPtr(Instruction *I,
BasicBlock::iterator
FastISel::SelectInstructions(BasicBlock::iterator Begin,
BasicBlock::iterator End,
DenseMap<const Value*, unsigned> &ValueMap) {
DenseMap<const Value*, unsigned> &ValueMap,
MachineBasicBlock *mbb) {
MBB = mbb;
BasicBlock::iterator I = Begin;
for (; I != End; ++I) {
@ -108,7 +111,7 @@ FastISel::SelectInstructions(BasicBlock::iterator Begin,
if (BI->isUnconditional()) {
MachineFunction::iterator NextMBB =
next(MachineFunction::iterator(MBB));
if (NextMBB != MF->end() &&
if (NextMBB != MF.end() &&
NextMBB->getBasicBlock() == BI->getSuccessor(0)) {
MBB->addSuccessor(NextMBB);
break;
@ -127,6 +130,10 @@ FastISel::SelectInstructions(BasicBlock::iterator Begin,
return I;
}
FastISel::FastISel(MachineFunction &mf)
: MF(mf), MRI(mf.getRegInfo()), TII(*mf.getTarget().getInstrInfo()) {
}
FastISel::~FastISel() {}
unsigned FastISel::FastEmit_(MVT::SimpleValueType, ISD::NodeType) {
@ -145,11 +152,10 @@ unsigned FastISel::FastEmit_rr(MVT::SimpleValueType, ISD::NodeType,
unsigned FastISel::FastEmitInst_(unsigned MachineInstOpcode,
const TargetRegisterClass* RC) {
MachineRegisterInfo &MRI = MF->getRegInfo();
unsigned ResultReg = MRI.createVirtualRegister(RC);
const TargetInstrDesc &II = TII->get(MachineInstOpcode);
const TargetInstrDesc &II = TII.get(MachineInstOpcode);
MachineInstr *MI = BuildMI(*MF, II, ResultReg);
MachineInstr *MI = BuildMI(MF, II, ResultReg);
MBB->push_back(MI);
return ResultReg;
}
@ -157,11 +163,10 @@ unsigned FastISel::FastEmitInst_(unsigned MachineInstOpcode,
unsigned FastISel::FastEmitInst_r(unsigned MachineInstOpcode,
const TargetRegisterClass *RC,
unsigned Op0) {
MachineRegisterInfo &MRI = MF->getRegInfo();
unsigned ResultReg = MRI.createVirtualRegister(RC);
const TargetInstrDesc &II = TII->get(MachineInstOpcode);
const TargetInstrDesc &II = TII.get(MachineInstOpcode);
MachineInstr *MI = BuildMI(*MF, II, ResultReg).addReg(Op0);
MachineInstr *MI = BuildMI(MF, II, ResultReg).addReg(Op0);
MBB->push_back(MI);
return ResultReg;
}
@ -169,11 +174,10 @@ unsigned FastISel::FastEmitInst_r(unsigned MachineInstOpcode,
unsigned FastISel::FastEmitInst_rr(unsigned MachineInstOpcode,
const TargetRegisterClass *RC,
unsigned Op0, unsigned Op1) {
MachineRegisterInfo &MRI = MF->getRegInfo();
unsigned ResultReg = MRI.createVirtualRegister(RC);
const TargetInstrDesc &II = TII->get(MachineInstOpcode);
const TargetInstrDesc &II = TII.get(MachineInstOpcode);
MachineInstr *MI = BuildMI(*MF, II, ResultReg).addReg(Op0).addReg(Op1);
MachineInstr *MI = BuildMI(MF, II, ResultReg).addReg(Op0).addReg(Op1);
MBB->push_back(MI);
return ResultReg;
}

6
lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
View File

@ -5111,9 +5111,9 @@ void SelectionDAGISel::BuildSelectionDAG(SelectionDAG &DAG, BasicBlock *LLVMBB,
!BB->isLandingPad() &&
isa<BranchInst>(LLVMBB->getTerminator()) &&
cast<BranchInst>(LLVMBB->getTerminator())->isUnconditional()) {
if (FastISel *F = TLI.createFastISel(BB, &FuncInfo.MF,
TLI.getTargetMachine().getInstrInfo())) {
Begin = F->SelectInstructions(Begin, LLVMBB->end(), FuncInfo.ValueMap);
if (FastISel *F = TLI.createFastISel(FuncInfo.MF)) {
Begin = F->SelectInstructions(Begin, LLVMBB->end(),
FuncInfo.ValueMap, BB);
// Clean up the FastISel object. TODO: Reorganize what data is
// stored in the FastISel class itself and what is merely passed

5
lib/Target/X86/X86FastISel.h
View File

@ -18,14 +18,11 @@
namespace llvm {
class FastISel;
class MachineBasicBlock;
class MachineFunction;
class TargetInstrInfo;
namespace X86 {
FastISel *createFastISel(MachineBasicBlock *mbb, MachineFunction *mf,
const TargetInstrInfo *tii);
FastISel *createFastISel(MachineFunction &mf);
} // namespace X86

6
lib/Target/X86/X86ISelLowering.cpp
View File

@ -1872,10 +1872,8 @@ bool X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Call,
return false;
}
FastISel *X86TargetLowering::createFastISel(MachineBasicBlock *mbb,
MachineFunction *mf,
const TargetInstrInfo *tii) {
return X86::createFastISel(mbb, mf, tii);
FastISel *X86TargetLowering::createFastISel(MachineFunction &mf) {
return X86::createFastISel(mf);
}

4
lib/Target/X86/X86ISelLowering.h
View File

@ -469,9 +469,7 @@ namespace llvm {
/// createFastISel - This method returns a target specific FastISel object,
/// or null if the target does not support "fast" ISel.
virtual FastISel *createFastISel(MachineBasicBlock *mbb,
MachineFunction *mf,
const TargetInstrInfo *tii);
virtual FastISel *createFastISel(MachineFunction &mf);
private:
/// Subtarget - Keep a pointer to the X86Subtarget around so that we can

8
utils/TableGen/FastISelEmitter.cpp
View File

@ -295,16 +295,14 @@ void FastISelEmitter::run(std::ostream &OS) {
OS << ");\n";
}
OS << "public:\n";
OS << " FastISel(MachineBasicBlock *mbb, MachineFunction *mf, ";
OS << "const TargetInstrInfo *tii) : llvm::FastISel(mbb, mf, tii) {}\n";
OS << " explicit FastISel(MachineFunction &mf) : llvm::FastISel(mf) {}\n";
OS << "};\n";
OS << "\n";
// Define the target FastISel creation function.
OS << "llvm::FastISel *" << InstNS
<< "createFastISel(MachineBasicBlock *mbb, MachineFunction *mf, ";
OS << "const TargetInstrInfo *tii) {\n";
OS << " return new " << InstNS << "FastISel(mbb, mf, tii);\n";
<< "createFastISel(MachineFunction &mf) {\n";
OS << " return new " << InstNS << "FastISel(mf);\n";
OS << "}\n";
OS << "\n";