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handle case where a register class is specified

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112842 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach 2010-09-02 18:18:52 +00:00
parent e7c1416263
commit bb5a039b76
1 changed files with 4 additions and 5 deletions
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9
lib/Target/TargetRegisterInfo.cpp
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@ -74,12 +74,11 @@ BitVector TargetRegisterInfo::getAllocatableSet(const MachineFunction &MF,
BitVector Allocatable(NumRegs);
if (RC) {
getAllocatableSetForRC(MF, RC, Allocatable);
return Allocatable;
}
for (TargetRegisterInfo::regclass_iterator I = regclass_begin(),
} else {
for (TargetRegisterInfo::regclass_iterator I = regclass_begin(),
E = regclass_end(); I != E; ++I)
getAllocatableSetForRC(MF, *I, Allocatable);
getAllocatableSetForRC(MF, *I, Allocatable);
}
// Mask out the reserved registers
BitVector Reserved = getReservedRegs(MF);