6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-06-26 10:29:57 +00:00
Code Issues Projects Releases Wiki Activity

[X86] Fix incorrect/inefficient pushw encodings for x86-64 targets

Browse Source 
Correctly support assembling "pushw $imm8" on x86-64 targets. 
Also some cleanup of the PUSH instructions (PUSH64i16 and PUSHi16 actually
represent the same instruction)

This fixes PR23996

Patch by: david.l.kreitzer@intel.com
Differential Revision: http://reviews.llvm.org/D10878

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241404 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Michael Kuperstein 2015-07-05 10:25:41 +00:00
parent a2a3583415
commit bb803fd76e
5 changed files with 49 additions and 9 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
View File

@ -220,7 +220,6 @@ static unsigned getRelaxedOpcodeArith(unsigned Op) {
case X86::PUSH32i8: return X86::PUSHi32;
case X86::PUSH16i8: return X86::PUSHi16;
case X86::PUSH64i8: return X86::PUSH64i32;
case X86::PUSH64i16: return X86::PUSH64i32;
}
}

12
lib/Target/X86/X86InstrInfo.td
View File

@ -1028,14 +1028,13 @@ def PUSH32rmm: I<0xFF, MRM6m, (outs), (ins i32mem:$src), "push{l}\t$src",[],
IIC_PUSH_MEM>, OpSize32, Requires<[Not64BitMode]>;
def PUSH16i8 : Ii8<0x6a, RawFrm, (outs), (ins i16i8imm:$imm),
"push{w}\t$imm", [], IIC_PUSH_IMM>, OpSize16,
Requires<[Not64BitMode]>;
"push{w}\t$imm", [], IIC_PUSH_IMM>, OpSize16;
def PUSHi16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
"push{w}\t$imm", [], IIC_PUSH_IMM>, OpSize16;
def PUSH32i8 : Ii8<0x6a, RawFrm, (outs), (ins i32i8imm:$imm),
"push{l}\t$imm", [], IIC_PUSH_IMM>, OpSize32,
Requires<[Not64BitMode]>;
def PUSHi16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
"push{w}\t$imm", [], IIC_PUSH_IMM>, OpSize16,
Requires<[Not64BitMode]>;
def PUSHi32 : Ii32<0x68, RawFrm, (outs), (ins i32imm:$imm),
"push{l}\t$imm", [], IIC_PUSH_IMM>, OpSize32,
Requires<[Not64BitMode]>;
@ -1081,9 +1080,6 @@ let Defs = [RSP], Uses = [RSP], hasSideEffects = 0, mayStore = 1,
SchedRW = [WriteStore] in {
def PUSH64i8 : Ii8<0x6a, RawFrm, (outs), (ins i64i8imm:$imm),
"push{q}\t$imm", [], IIC_PUSH_IMM>, Requires<[In64BitMode]>;
def PUSH64i16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
"push{w}\t$imm", [], IIC_PUSH_IMM>, OpSize16,
Requires<[In64BitMode]>;
def PUSH64i32 : Ii32S<0x68, RawFrm, (outs), (ins i64i32imm:$imm),
"push{q}\t$imm", [], IIC_PUSH_IMM>, OpSize32,
Requires<[In64BitMode]>;

8
test/MC/ELF/relax-arith.s
View File

@ -115,3 +115,11 @@ bar:
cmpl $foo, bar
cmp $foo, %rbx
cmpq $foo, bar
// CHECK: Disassembly of section push:
// CHECK-NEXT: push:
// CHECK-NEXT: 0: 66 68 00 00 pushw $0
// CHECK-NEXT: 4: 68 00 00 00 00 pushq $0
.section push,"x"
pushw $foo
push $foo

12
test/MC/ELF/relax-arith2.s
View File

@ -116,3 +116,15 @@ bar:
cmpl $1, bar
cmp $-1, %rbx
cmpq $42, bar
// CHECK: Disassembly of section push:
// CHECK-NEXT: push:
// CHECK-NEXT: 0: 66 6a 80 pushw $-128
// CHECK-NEXT: 3: 66 6a 7f pushw $127
// CHECK-NEXT: 6: 6a 80 pushq $-128
// CHECK-NEXT: 8: 6a 7f pushq $127
.section push,"x"
pushw $-128
pushw $127
push $-128
push $127

25
test/MC/ELF/relax-arith4.s Normal file
View File

@ -0,0 +1,25 @@
// RUN: llvm-mc -filetype=obj -triple i686-pc-linux-gnu %s -o - | llvm-objdump -d - | FileCheck %s
// Test for proper instruction relaxation behavior for the push $imm
// instruction forms. This is the 32-bit version of the push $imm tests from
// relax-arith.s and relax-arith2.s.
// CHECK: Disassembly of section push8:
// CHECK-NEXT: push8:
// CHECK-NEXT: 0: 66 6a 80 pushw $-128
// CHECK-NEXT: 3: 66 6a 7f pushw $127
// CHECK-NEXT: 6: 6a 80 pushl $-128
// CHECK-NEXT: 8: 6a 7f pushl $127
.section push8,"x"
pushw $-128
pushw $127
push $-128
push $127
// CHECK: Disassembly of section push32:
// CHECK-NEXT: push32:
// CHECK-NEXT: 0: 66 68 00 00 pushw $0
// CHECK-NEXT: 4: 68 00 00 00 00 pushl $0
.section push32,"x"
pushw $foo
push $foo