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The list-td and list-tdrr schedulers don't yet support physreg
scheduling dependencies. Add assertion checks to help catch this. It appears the Mips target defaults to list-td, and it has a regression test that uses a physreg dependence. Such code was liable to be miscompiled, and now evokes an assertion failure. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62177 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -140,8 +140,12 @@ void ScheduleDAGList::ScheduleNodeTopDown(SUnit *SU, unsigned CurCycle) {
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// Top down: release successors.
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for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
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I != E; ++I)
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I != E; ++I) {
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assert(!I->isAssignedRegDep() &&
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"The list-td scheduler doesn't yet support physreg dependencies!");
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ReleaseSucc(SU, *I);
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}
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SU->isScheduled = true;
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AvailableQueue->ScheduledNode(SU);
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@ -816,8 +816,12 @@ void ScheduleDAGRRList::ScheduleNodeTopDown(SUnit *SU, unsigned CurCycle) {
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// Top down: release successors
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for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
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I != E; ++I)
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I != E; ++I) {
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assert(!I->isAssignedRegDep() &&
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"The list-tdrr scheduler doesn't yet support physreg dependencies!");
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ReleaseSucc(SU, &*I);
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}
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SU->isScheduled = true;
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AvailableQueue->ScheduledNode(SU);
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@ -1,10 +1,11 @@
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; RUN: llvm-as < %s | llc -pre-RA-sched=default
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; RUN: llvm-as < %s | llc -pre-RA-sched=list-td
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; RUN: llvm-as < %s | llc -pre-RA-sched=list-tdrr
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; RUN: llvm-as < %s | llc -pre-RA-sched=list-burr
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; RUN: llvm-as < %s | llc -pre-RA-sched=fast
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; PR859
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; The top-down schedulers are excluded here because they don't yet support
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; targets that use physreg defs.
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declare i32 @printf(i8*, i32, float)
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define i32 @testissue(i32 %i, float %x, float %y) {
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@ -1,6 +1,7 @@
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; RUN: llvm-as < %s | llc -march=mips -f -o %t
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; RUN: grep {c\\..*\\.s} %t | count 3
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; RUN: grep {bc1\[tf\]} %t | count 3
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; XFAIL: *
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target datalayout = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64"
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target triple = "mipsallegrexel-psp-elf"
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