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Cleanup IA64ISD, tell the graph drawer what the symbolic names for the enums are.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25324 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -94,6 +94,15 @@ IA64TargetLowering::IA64TargetLowering(TargetMachine &TM)
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addLegalFPImmediate(+1.0);
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}
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const char *IA64TargetLowering::getTargetNodeName(unsigned Opcode) const {
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switch (Opcode) {
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default: return 0;
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case IA64ISD::GETFD: return "IA64ISD::GETFD";
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case IA64ISD::BRCALL: return "IA64ISD::BRCALL";
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}
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}
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/// isFloatingPointZero - Return true if this is 0.0 or -0.0.
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static bool isFloatingPointZero(SDOperand Op) {
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if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
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@ -25,20 +25,6 @@ namespace llvm {
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// Start the numbering where the builting ops and target ops leave off.
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FIRST_NUMBER = ISD::BUILTIN_OP_END+IA64::INSTRUCTION_LIST_END,
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/// FSEL - Traditional three-operand fsel node.
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///
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FSEL,
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/// FCFID - The FCFID instruction, taking an f64 operand and producing
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/// and f64 value containing the FP representation of the integer that
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/// was temporarily in the f64 operand.
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FCFID,
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/// FCTI[D,W]Z - The FCTIDZ and FCTIWZ instructions, taking an f32 or f64
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/// operand, producing an f64 value containing the integer representation
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/// of that FP value.
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FCTIDZ, FCTIWZ,
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/// GETFD - the getf.d instruction takes a floating point operand and
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/// returns its 64-bit memory representation as an i64
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GETFD,
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@ -63,6 +49,8 @@ namespace llvm {
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///
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// XXX virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
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const char *getTargetNodeName(unsigned Opcode) const;
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/// LowerArguments - This hook must be implemented to indicate how we should
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/// lower the arguments for the specified function, into the specified DAG.
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virtual std::vector<SDOperand>
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