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Reimplement r114460 in target-independent DAGCombine rather than target-dependent, by using
the predicate to discover the number of sign bits. Enhance X86's target lowering to provide a useful response to this query. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114473 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1424,6 +1424,20 @@ SDValue DAGCombiner::visitADD(SDNode *N) {
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N0.getOperand(0).getOperand(1),
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N0.getOperand(0).getOperand(1),
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N0.getOperand(1)));
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N0.getOperand(1)));
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if (N1.getOpcode() == ISD::AND) {
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SDValue AndOp0 = N1.getOperand(0);
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ConstantSDNode *AndOp1 = dyn_cast<ConstantSDNode>(N1->getOperand(1));
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unsigned NumSignBits = DAG.ComputeNumSignBits(AndOp0);
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unsigned DestBits = VT.getScalarType().getSizeInBits();
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// (add z, (and (sbbl x, x), 1)) -> (sub z, (sbbl x, x))
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// and similar xforms where the inner op is either ~0 or 0.
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if (NumSignBits == DestBits && AndOp1 && AndOp1->isOne()) {
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DebugLoc DL = N->getDebugLoc();
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return DAG.getNode(ISD::SUB, DL, VT, N->getOperand(0), AndOp0);
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}
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}
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return SDValue();
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return SDValue();
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}
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}
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@ -1021,7 +1021,6 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
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setTargetDAGCombine(ISD::OR);
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setTargetDAGCombine(ISD::OR);
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setTargetDAGCombine(ISD::STORE);
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setTargetDAGCombine(ISD::STORE);
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setTargetDAGCombine(ISD::ZERO_EXTEND);
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setTargetDAGCombine(ISD::ZERO_EXTEND);
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setTargetDAGCombine(ISD::ADD);
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if (Subtarget->is64Bit())
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if (Subtarget->is64Bit())
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setTargetDAGCombine(ISD::MUL);
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setTargetDAGCombine(ISD::MUL);
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@ -9980,6 +9979,16 @@ void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
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}
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}
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}
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}
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unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
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unsigned Depth) const {
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// SETCC_CARRY sets the dest to ~0 for true or 0 for false.
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if (Op.getOpcode() == X86ISD::SETCC_CARRY)
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return Op.getValueType().getScalarType().getSizeInBits();
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// Fallback case.
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return 1;
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}
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/// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
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/// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
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/// node is a GlobalAddress + offset.
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/// node is a GlobalAddress + offset.
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bool X86TargetLowering::isGAPlusOffset(SDNode *N,
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bool X86TargetLowering::isGAPlusOffset(SDNode *N,
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@ -10454,27 +10463,6 @@ static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
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return SDValue();
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return SDValue();
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}
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}
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/// PerformAddCombine - Optimize ADD when combined with X86 opcodes.
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static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
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TargetLowering::DAGCombinerInfo &DCI) {
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if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
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return SDValue();
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EVT VT = N->getValueType(0);
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SDValue Op1 = N->getOperand(1);
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if (Op1->getOpcode() == ISD::AND) {
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SDValue AndOp0 = Op1->getOperand(0);
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ConstantSDNode *AndOp1 = dyn_cast<ConstantSDNode>(Op1->getOperand(1));
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// (add z, (and (sbbl x, x), 1)) -> (sub z, (sbbl x, x))
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if (AndOp0->getOpcode() == X86ISD::SETCC_CARRY &&
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AndOp1 && AndOp1->getZExtValue() == 1) {
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DebugLoc DL = N->getDebugLoc();
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return DAG.getNode(ISD::SUB, DL, VT, N->getOperand(0), AndOp0);
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}
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}
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return SDValue();
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}
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/// PerformMulCombine - Optimize a single multiply with constant into two
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/// PerformMulCombine - Optimize a single multiply with constant into two
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/// in order to implement it with two cheaper instructions, e.g.
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/// in order to implement it with two cheaper instructions, e.g.
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@ -10961,7 +10949,6 @@ SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
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return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, *this);
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return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, *this);
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case ISD::SELECT: return PerformSELECTCombine(N, DAG, Subtarget);
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case ISD::SELECT: return PerformSELECTCombine(N, DAG, Subtarget);
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case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI);
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case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI);
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case ISD::ADD: return PerformAddCombine(N, DAG, DCI);
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case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
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case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
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case ISD::SHL:
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case ISD::SHL:
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case ISD::SRA:
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case ISD::SRA:
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@ -523,6 +523,11 @@ namespace llvm {
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const SelectionDAG &DAG,
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const SelectionDAG &DAG,
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unsigned Depth = 0) const;
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unsigned Depth = 0) const;
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// ComputeNumSignBitsForTargetNode - Determine the number of bits in the
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// operation that are sign bits.
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virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
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unsigned Depth) const;
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virtual bool
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virtual bool
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isGAPlusOffset(SDNode *N, const GlobalValue* &GA, int64_t &Offset) const;
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isGAPlusOffset(SDNode *N, const GlobalValue* &GA, int64_t &Offset) const;
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