6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-08-05 13:26:55 +00:00
Code Issues Projects Releases Wiki Activity

Convert assert(0) to llvm_unreachable

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149961 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Craig Topper
2012-02-07 02:50:20 +00:00
parent c5de7fea7b
commit bc2198133a
42 changed files with 106 additions and 151 deletions
Download Patch File Download Diff File Expand all files Collapse all files

15
lib/Target/Hexagon/HexagonInstrInfo.cpp
View File

@@ -383,7 +383,7 @@ storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
.addFrameIndex(FI).addImm(0)
.addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
} else {
assert(0 && "Unimplemented");
llvm_unreachable("Unimplemented");
}
}
@@ -395,8 +395,7 @@ void HexagonInstrInfo::storeRegToAddr(
const TargetRegisterClass *RC,
SmallVectorImpl<MachineInstr*> &NewMIs) const
{
assert(0 && "Unimplemented");
return;
llvm_unreachable("Unimplemented");
}
@@ -427,7 +426,7 @@ loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
BuildMI(MBB, I, DL, get(Hexagon::LDriw_pred), DestReg)
.addFrameIndex(FI).addImm(0).addMemOperand(MMO);
} else {
assert(0 && "Can't store this register to stack slot");
llvm_unreachable("Can't store this register to stack slot");
}
}
@@ -436,7 +435,7 @@ void HexagonInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
SmallVectorImpl<MachineOperand> &Addr,
const TargetRegisterClass *RC,
SmallVectorImpl<MachineInstr*> &NewMIs) const {
assert(0 && "Unimplemented");
llvm_unreachable("Unimplemented");
}
@@ -823,7 +822,7 @@ PredicateInstruction(MachineInstr *MI,
} else if (MO.isImm()) {
MI->getOperand(oper+1).ChangeToImmediate(MO.getImm());
} else {
assert(false && "Unexpected operand type");
llvm_unreachable("Unexpected operand type");
}
}
@@ -1269,10 +1268,8 @@ isValidAutoIncImm(const EVT VT, const int Offset) const {
return (Offset >= Hexagon_MEMB_AUTOINC_MIN &&
Offset <= Hexagon_MEMB_AUTOINC_MAX);
}
assert(0 && "Not an auto-inc opc!");
return false;
llvm_unreachable("Not an auto-inc opc!");
}