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Basic 32-bit FP operations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113459 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -115,6 +115,7 @@ class ARMFastISel : public FastISel {
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virtual bool ARMSelectBranch(const Instruction *I);
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virtual bool ARMSelectCmp(const Instruction *I);
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virtual bool ARMSelectFPExt(const Instruction *I);
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virtual bool ARMSelectBinaryOp(const Instruction *I, unsigned ISDOpcode);
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// Utility routines.
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private:
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@ -740,6 +741,44 @@ bool ARMFastISel::ARMSelectFPExt(const Instruction *I) {
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return true;
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}
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bool ARMFastISel::ARMSelectBinaryOp(const Instruction *I, unsigned ISDOpcode) {
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// We can get here in the case when we want to use NEON for our fp
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// operations, but can't figure out how to. Just use the vfp instructions
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// if we have them.
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// FIXME: It'd be nice to use NEON instructions.
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if (!Subtarget->hasVFP2()) return false;
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EVT VT = TLI.getValueType(I->getType(), true);
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// In this case make extra sure we have a 32-bit floating point add.
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if (VT != MVT::f32) return false;
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unsigned Op1 = getRegForValue(I->getOperand(0));
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if (Op1 == 0) return false;
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unsigned Op2 = getRegForValue(I->getOperand(1));
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if (Op2 == 0) return false;
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unsigned Opc;
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switch (ISDOpcode) {
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default: return false;
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case ISD::FADD:
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Opc = ARM::VADDS;
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break;
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case ISD::FSUB:
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Opc = ARM::VSUBS;
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break;
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case ISD::FMUL:
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Opc = ARM::VMULS;
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break;
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}
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unsigned ResultReg = createResultReg(ARM::SPRRegisterClass);
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AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
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TII.get(Opc), ResultReg)
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.addReg(Op1).addReg(Op2));
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return true;
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}
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// TODO: SoftFP support.
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bool ARMFastISel::TargetSelectInstruction(const Instruction *I) {
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// No Thumb-1 for now.
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@ -757,6 +796,12 @@ bool ARMFastISel::TargetSelectInstruction(const Instruction *I) {
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return ARMSelectCmp(I);
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case Instruction::FPExt:
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return ARMSelectFPExt(I);
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case Instruction::FAdd:
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return ARMSelectBinaryOp(I, ISD::FADD);
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case Instruction::FSub:
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return ARMSelectBinaryOp(I, ISD::FSUB);
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case Instruction::FMul:
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return ARMSelectBinaryOp(I, ISD::FMUL);
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default: break;
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}
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return false;
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