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[ARM] Don't break alignment when combining base updates into load/stores.
r223862/r224203 tried to also combine base-updating load/stores. There was a mistake there: the alignment was added as is as an operand to the ARMISD::VLD/VST node. However, the VLD/VST selection logic doesn't care about less-than-standard alignment attributes. For example, no matter the alignment of a v2i64 load (say 1), SelectVLD picks VLD1q64 (because of the memory type). But VLD1q64 ("vld1.64 {dXX, dYY}") is 8-aligned, per ARMARMv7a 3.2.1. For the 1-aligned load, what we really want is VLD1q8. This commit introduces bitcasts if necessary, and changes the vld/vst type to one whose standard alignment matches the original load/store alignment. Differential Revision: http://reviews.llvm.org/D6759 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224754 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -8976,13 +8976,42 @@ static SDValue CombineBaseUpdate(SDNode *N,
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continue;
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continue;
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}
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}
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EVT AlignedVecTy = VecTy;
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// If this is a less-than-standard-aligned load/store, change the type to
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// match the standard alignment.
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// The alignment is overlooked when selecting _UPD variants; and it's
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// easier to introduce bitcasts here than fix that.
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// There are 3 ways to get to this base-update combine:
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// - intrinsics: they are assumed to be properly aligned (to the standard
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// alignment of the memory type), so we don't need to do anything.
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// - ARMISD::VLDx nodes: they are only generated from the aforementioned
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// intrinsics, so, likewise, there's nothing to do.
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// - generic load/store instructions: the alignment is specified as an
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// explicit operand, rather than implicitly as the standard alignment
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// of the memory type (like the intrisics). We need to change the
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// memory type to match the explicit alignment. That way, we don't
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// generate non-standard-aligned ARMISD::VLDx nodes.
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if (LSBaseSDNode *LSN = dyn_cast<LSBaseSDNode>(N)) {
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unsigned Alignment = LSN->getAlignment();
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if (Alignment == 0)
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Alignment = 1;
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if (Alignment < VecTy.getScalarSizeInBits() / 8) {
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MVT EltTy = MVT::getIntegerVT(Alignment * 8);
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assert(NumVecs == 1 && "Unexpected multi-element generic load/store.");
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assert(!isLaneOp && "Unexpected generic load/store lane.");
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unsigned NumElts = NumBytes / (EltTy.getSizeInBits() / 8);
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AlignedVecTy = MVT::getVectorVT(EltTy, NumElts);
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}
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}
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// Create the new updating load/store node.
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// Create the new updating load/store node.
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// First, create an SDVTList for the new updating node's results.
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// First, create an SDVTList for the new updating node's results.
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EVT Tys[6];
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EVT Tys[6];
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unsigned NumResultVecs = (isLoad ? NumVecs : 0);
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unsigned NumResultVecs = (isLoad ? NumVecs : 0);
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unsigned n;
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unsigned n;
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for (n = 0; n < NumResultVecs; ++n)
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for (n = 0; n < NumResultVecs; ++n)
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Tys[n] = VecTy;
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Tys[n] = AlignedVecTy;
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Tys[n++] = MVT::i32;
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Tys[n++] = MVT::i32;
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Tys[n] = MVT::Other;
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Tys[n] = MVT::Other;
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SDVTList SDTys = DAG.getVTList(makeArrayRef(Tys, NumResultVecs+2));
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SDVTList SDTys = DAG.getVTList(makeArrayRef(Tys, NumResultVecs+2));
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@ -9000,9 +9029,17 @@ static SDValue CombineBaseUpdate(SDNode *N,
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for (unsigned i = AddrOpIdx + 1; i < N->getNumOperands(); ++i)
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for (unsigned i = AddrOpIdx + 1; i < N->getNumOperands(); ++i)
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Ops.push_back(N->getOperand(i));
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Ops.push_back(N->getOperand(i));
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}
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}
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// If this is a non-standard-aligned store, the penultimate operand is the
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// stored value. Bitcast it to the aligned type.
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if (AlignedVecTy != VecTy && N->getOpcode() == ISD::STORE) {
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SDValue &StVal = Ops[Ops.size()-2];
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StVal = DAG.getNode(ISD::BITCAST, SDLoc(N), AlignedVecTy, StVal);
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}
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MemSDNode *MemInt = cast<MemSDNode>(N);
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MemSDNode *MemInt = cast<MemSDNode>(N);
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SDValue UpdN = DAG.getMemIntrinsicNode(NewOpc, SDLoc(N), SDTys,
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SDValue UpdN = DAG.getMemIntrinsicNode(NewOpc, SDLoc(N), SDTys,
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Ops, MemInt->getMemoryVT(),
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Ops, AlignedVecTy,
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MemInt->getMemOperand());
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MemInt->getMemOperand());
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// Update the uses.
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// Update the uses.
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@ -9010,6 +9047,14 @@ static SDValue CombineBaseUpdate(SDNode *N,
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for (unsigned i = 0; i < NumResultVecs; ++i) {
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for (unsigned i = 0; i < NumResultVecs; ++i) {
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NewResults.push_back(SDValue(UpdN.getNode(), i));
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NewResults.push_back(SDValue(UpdN.getNode(), i));
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}
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}
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// If this is an non-standard-aligned load, the first result is the loaded
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// value. Bitcast it to the expected result type.
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if (AlignedVecTy != VecTy && N->getOpcode() == ISD::LOAD) {
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SDValue &LdVal = NewResults[0];
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LdVal = DAG.getNode(ISD::BITCAST, SDLoc(N), VecTy, LdVal);
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}
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NewResults.push_back(SDValue(UpdN.getNode(), NumResultVecs+1)); // chain
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NewResults.push_back(SDValue(UpdN.getNode(), NumResultVecs+1)); // chain
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DCI.CombineTo(N, NewResults);
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DCI.CombineTo(N, NewResults);
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DCI.CombineTo(User, SDValue(UpdN.getNode(), NumResultVecs));
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DCI.CombineTo(User, SDValue(UpdN.getNode(), NumResultVecs));
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@ -46,8 +46,8 @@ entry:
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; CHECK: movw [[REG2:r[0-9]+]], #16716
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; CHECK: movw [[REG2:r[0-9]+]], #16716
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; CHECK: movt [[REG2:r[0-9]+]], #72
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; CHECK: movt [[REG2:r[0-9]+]], #72
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; CHECK: str [[REG2]], [r0, #32]
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; CHECK: str [[REG2]], [r0, #32]
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; CHECK: vld1.64 {d{{[0-9]+}}, d{{[0-9]+}}}, [r1]!
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; CHECK: vld1.8 {d{{[0-9]+}}, d{{[0-9]+}}}, [r1]!
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; CHECK: vst1.64 {d{{[0-9]+}}, d{{[0-9]+}}}, [r0]!
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; CHECK: vst1.8 {d{{[0-9]+}}, d{{[0-9]+}}}, [r0]!
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; CHECK: vld1.8 {d{{[0-9]+}}, d{{[0-9]+}}}, [r1]
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; CHECK: vld1.8 {d{{[0-9]+}}, d{{[0-9]+}}}, [r1]
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; CHECK: vst1.8 {d{{[0-9]+}}, d{{[0-9]+}}}, [r0]
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; CHECK: vst1.8 {d{{[0-9]+}}, d{{[0-9]+}}}, [r0]
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tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %C, i8* getelementptr inbounds ([36 x i8]* @.str2, i64 0, i64 0), i64 36, i32 1, i1 false)
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tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %C, i8* getelementptr inbounds ([36 x i8]* @.str2, i64 0, i64 0), i64 36, i32 1, i1 false)
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@ -57,8 +57,8 @@ entry:
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define void @t3(i8* nocapture %C) nounwind {
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define void @t3(i8* nocapture %C) nounwind {
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entry:
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entry:
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; CHECK-LABEL: t3:
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; CHECK-LABEL: t3:
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; CHECK: vld1.64 {d{{[0-9]+}}, d{{[0-9]+}}}, [r1]!
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; CHECK: vld1.8 {d{{[0-9]+}}, d{{[0-9]+}}}, [r1]!
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; CHECK: vst1.64 {d{{[0-9]+}}, d{{[0-9]+}}}, [r0]!
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; CHECK: vst1.8 {d{{[0-9]+}}, d{{[0-9]+}}}, [r0]!
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; CHECK: vld1.8 {d{{[0-9]+}}}, [r1]
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; CHECK: vld1.8 {d{{[0-9]+}}}, [r1]
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; CHECK: vst1.8 {d{{[0-9]+}}}, [r0]
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; CHECK: vst1.8 {d{{[0-9]+}}}, [r0]
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tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %C, i8* getelementptr inbounds ([24 x i8]* @.str3, i64 0, i64 0), i64 24, i32 1, i1 false)
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tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %C, i8* getelementptr inbounds ([24 x i8]* @.str3, i64 0, i64 0), i64 24, i32 1, i1 false)
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@ -69,7 +69,7 @@ define void @t4(i8* nocapture %C) nounwind {
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entry:
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entry:
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; CHECK-LABEL: t4:
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; CHECK-LABEL: t4:
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; CHECK: vld1.8 {[[REG3:d[0-9]+]], [[REG4:d[0-9]+]]}, [r1]
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; CHECK: vld1.8 {[[REG3:d[0-9]+]], [[REG4:d[0-9]+]]}, [r1]
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; CHECK: vst1.64 {[[REG3]], [[REG4]]}, [r0]!
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; CHECK: vst1.8 {[[REG3]], [[REG4]]}, [r0]!
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; CHECK: strh [[REG5:r[0-9]+]], [r0]
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; CHECK: strh [[REG5:r[0-9]+]], [r0]
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tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %C, i8* getelementptr inbounds ([18 x i8]* @.str4, i64 0, i64 0), i64 18, i32 1, i1 false)
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tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %C, i8* getelementptr inbounds ([18 x i8]* @.str4, i64 0, i64 0), i64 18, i32 1, i1 false)
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ret void
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ret void
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@ -31,7 +31,7 @@ define <4 x i16> @load_v4i16(<4 x i16>** %ptr) {
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define <4 x i16> @load_v4i16_update(<4 x i16>** %ptr) {
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define <4 x i16> @load_v4i16_update(<4 x i16>** %ptr) {
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;CHECK-LABEL: load_v4i16_update:
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;CHECK-LABEL: load_v4i16_update:
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;CHECK: vld1.16 {{{d[0-9]+}}}, [{{r[0-9]+}}]!
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;CHECK: vld1.8 {{{d[0-9]+}}}, [{{r[0-9]+}}]!
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%A = load <4 x i16>** %ptr
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%A = load <4 x i16>** %ptr
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%lA = load <4 x i16>* %A, align 1
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%lA = load <4 x i16>* %A, align 1
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%inc = getelementptr <4 x i16>* %A, i34 1
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%inc = getelementptr <4 x i16>* %A, i34 1
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@ -49,7 +49,7 @@ define <2 x i32> @load_v2i32(<2 x i32>** %ptr) {
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define <2 x i32> @load_v2i32_update(<2 x i32>** %ptr) {
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define <2 x i32> @load_v2i32_update(<2 x i32>** %ptr) {
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;CHECK-LABEL: load_v2i32_update:
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;CHECK-LABEL: load_v2i32_update:
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;CHECK: vld1.32 {{{d[0-9]+}}}, [{{r[0-9]+}}]!
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;CHECK: vld1.8 {{{d[0-9]+}}}, [{{r[0-9]+}}]!
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%A = load <2 x i32>** %ptr
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%A = load <2 x i32>** %ptr
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%lA = load <2 x i32>* %A, align 1
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%lA = load <2 x i32>* %A, align 1
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%inc = getelementptr <2 x i32>* %A, i32 1
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%inc = getelementptr <2 x i32>* %A, i32 1
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@ -67,7 +67,7 @@ define <2 x float> @load_v2f32(<2 x float>** %ptr) {
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define <2 x float> @load_v2f32_update(<2 x float>** %ptr) {
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define <2 x float> @load_v2f32_update(<2 x float>** %ptr) {
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;CHECK-LABEL: load_v2f32_update:
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;CHECK-LABEL: load_v2f32_update:
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;CHECK: vld1.32 {{{d[0-9]+}}}, [{{r[0-9]+}}]!
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;CHECK: vld1.8 {{{d[0-9]+}}}, [{{r[0-9]+}}]!
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%A = load <2 x float>** %ptr
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%A = load <2 x float>** %ptr
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%lA = load <2 x float>* %A, align 1
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%lA = load <2 x float>* %A, align 1
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%inc = getelementptr <2 x float>* %A, i32 1
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%inc = getelementptr <2 x float>* %A, i32 1
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@ -85,7 +85,7 @@ define <1 x i64> @load_v1i64(<1 x i64>** %ptr) {
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define <1 x i64> @load_v1i64_update(<1 x i64>** %ptr) {
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define <1 x i64> @load_v1i64_update(<1 x i64>** %ptr) {
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;CHECK-LABEL: load_v1i64_update:
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;CHECK-LABEL: load_v1i64_update:
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;CHECK: vld1.64 {{{d[0-9]+}}}, [{{r[0-9]+}}]!
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;CHECK: vld1.8 {{{d[0-9]+}}}, [{{r[0-9]+}}]!
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%A = load <1 x i64>** %ptr
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%A = load <1 x i64>** %ptr
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%lA = load <1 x i64>* %A, align 1
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%lA = load <1 x i64>* %A, align 1
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%inc = getelementptr <1 x i64>* %A, i31 1
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%inc = getelementptr <1 x i64>* %A, i31 1
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@ -121,7 +121,7 @@ define <8 x i16> @load_v8i16(<8 x i16>** %ptr) {
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define <8 x i16> @load_v8i16_update(<8 x i16>** %ptr) {
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define <8 x i16> @load_v8i16_update(<8 x i16>** %ptr) {
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;CHECK-LABEL: load_v8i16_update:
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;CHECK-LABEL: load_v8i16_update:
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;CHECK: vld1.16 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]!
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;CHECK: vld1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]!
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%A = load <8 x i16>** %ptr
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%A = load <8 x i16>** %ptr
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%lA = load <8 x i16>* %A, align 1
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%lA = load <8 x i16>* %A, align 1
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%inc = getelementptr <8 x i16>* %A, i38 1
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%inc = getelementptr <8 x i16>* %A, i38 1
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@ -139,7 +139,7 @@ define <4 x i32> @load_v4i32(<4 x i32>** %ptr) {
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define <4 x i32> @load_v4i32_update(<4 x i32>** %ptr) {
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define <4 x i32> @load_v4i32_update(<4 x i32>** %ptr) {
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;CHECK-LABEL: load_v4i32_update:
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;CHECK-LABEL: load_v4i32_update:
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;CHECK: vld1.32 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]!
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;CHECK: vld1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]!
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%A = load <4 x i32>** %ptr
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%A = load <4 x i32>** %ptr
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%lA = load <4 x i32>* %A, align 1
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%lA = load <4 x i32>* %A, align 1
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%inc = getelementptr <4 x i32>* %A, i34 1
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%inc = getelementptr <4 x i32>* %A, i34 1
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@ -157,7 +157,7 @@ define <4 x float> @load_v4f32(<4 x float>** %ptr) {
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define <4 x float> @load_v4f32_update(<4 x float>** %ptr) {
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define <4 x float> @load_v4f32_update(<4 x float>** %ptr) {
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;CHECK-LABEL: load_v4f32_update:
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;CHECK-LABEL: load_v4f32_update:
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;CHECK: vld1.32 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]!
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;CHECK: vld1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]!
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%A = load <4 x float>** %ptr
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%A = load <4 x float>** %ptr
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%lA = load <4 x float>* %A, align 1
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%lA = load <4 x float>* %A, align 1
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%inc = getelementptr <4 x float>* %A, i34 1
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%inc = getelementptr <4 x float>* %A, i34 1
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@ -175,7 +175,7 @@ define <2 x i64> @load_v2i64(<2 x i64>** %ptr) {
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define <2 x i64> @load_v2i64_update(<2 x i64>** %ptr) {
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define <2 x i64> @load_v2i64_update(<2 x i64>** %ptr) {
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;CHECK-LABEL: load_v2i64_update:
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;CHECK-LABEL: load_v2i64_update:
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;CHECK: vld1.64 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]!
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;CHECK: vld1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]!
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%A = load <2 x i64>** %ptr
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%A = load <2 x i64>** %ptr
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%lA = load <2 x i64>* %A, align 1
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%lA = load <2 x i64>* %A, align 1
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%inc = getelementptr <2 x i64>* %A, i32 1
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%inc = getelementptr <2 x i64>* %A, i32 1
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@ -183,6 +183,47 @@ define <2 x i64> @load_v2i64_update(<2 x i64>** %ptr) {
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ret <2 x i64> %lA
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ret <2 x i64> %lA
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}
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}
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; Make sure we change the type to match alignment if necessary.
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define <2 x i64> @load_v2i64_update_aligned2(<2 x i64>** %ptr) {
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;CHECK-LABEL: load_v2i64_update_aligned2:
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;CHECK: vld1.16 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]!
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%A = load <2 x i64>** %ptr
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%lA = load <2 x i64>* %A, align 2
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%inc = getelementptr <2 x i64>* %A, i32 1
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store <2 x i64>* %inc, <2 x i64>** %ptr
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ret <2 x i64> %lA
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}
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define <2 x i64> @load_v2i64_update_aligned4(<2 x i64>** %ptr) {
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;CHECK-LABEL: load_v2i64_update_aligned4:
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;CHECK: vld1.32 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]!
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%A = load <2 x i64>** %ptr
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%lA = load <2 x i64>* %A, align 4
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%inc = getelementptr <2 x i64>* %A, i32 1
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store <2 x i64>* %inc, <2 x i64>** %ptr
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ret <2 x i64> %lA
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}
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define <2 x i64> @load_v2i64_update_aligned8(<2 x i64>** %ptr) {
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|
;CHECK-LABEL: load_v2i64_update_aligned8:
|
||||||
|
;CHECK: vld1.64 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}:64]!
|
||||||
|
%A = load <2 x i64>** %ptr
|
||||||
|
%lA = load <2 x i64>* %A, align 8
|
||||||
|
%inc = getelementptr <2 x i64>* %A, i32 1
|
||||||
|
store <2 x i64>* %inc, <2 x i64>** %ptr
|
||||||
|
ret <2 x i64> %lA
|
||||||
|
}
|
||||||
|
|
||||||
|
define <2 x i64> @load_v2i64_update_aligned16(<2 x i64>** %ptr) {
|
||||||
|
;CHECK-LABEL: load_v2i64_update_aligned16:
|
||||||
|
;CHECK: vld1.64 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}:128]!
|
||||||
|
%A = load <2 x i64>** %ptr
|
||||||
|
%lA = load <2 x i64>* %A, align 16
|
||||||
|
%inc = getelementptr <2 x i64>* %A, i32 1
|
||||||
|
store <2 x i64>* %inc, <2 x i64>** %ptr
|
||||||
|
ret <2 x i64> %lA
|
||||||
|
}
|
||||||
|
|
||||||
; Make sure we don't break smaller-than-dreg extloads.
|
; Make sure we don't break smaller-than-dreg extloads.
|
||||||
define <4 x i32> @zextload_v8i8tov8i32(<4 x i8>** %ptr) {
|
define <4 x i32> @zextload_v8i8tov8i32(<4 x i8>** %ptr) {
|
||||||
;CHECK-LABEL: zextload_v8i8tov8i32:
|
;CHECK-LABEL: zextload_v8i8tov8i32:
|
||||||
@ -190,7 +231,7 @@ define <4 x i32> @zextload_v8i8tov8i32(<4 x i8>** %ptr) {
|
|||||||
;CHECK: vmovl.u8 {{q[0-9]+}}, {{d[0-9]+}}
|
;CHECK: vmovl.u8 {{q[0-9]+}}, {{d[0-9]+}}
|
||||||
;CHECK: vmovl.u16 {{q[0-9]+}}, {{d[0-9]+}}
|
;CHECK: vmovl.u16 {{q[0-9]+}}, {{d[0-9]+}}
|
||||||
%A = load <4 x i8>** %ptr
|
%A = load <4 x i8>** %ptr
|
||||||
%lA = load <4 x i8>* %A, align 1
|
%lA = load <4 x i8>* %A, align 4
|
||||||
%zlA = zext <4 x i8> %lA to <4 x i32>
|
%zlA = zext <4 x i8> %lA to <4 x i32>
|
||||||
ret <4 x i32> %zlA
|
ret <4 x i32> %zlA
|
||||||
}
|
}
|
||||||
|
@ -31,7 +31,7 @@ define void @store_v4i16(<4 x i16>** %ptr, <4 x i16> %val) {
|
|||||||
|
|
||||||
define void @store_v4i16_update(<4 x i16>** %ptr, <4 x i16> %val) {
|
define void @store_v4i16_update(<4 x i16>** %ptr, <4 x i16> %val) {
|
||||||
;CHECK-LABEL: store_v4i16_update:
|
;CHECK-LABEL: store_v4i16_update:
|
||||||
;CHECK: vst1.16 {{{d[0-9]+}}}, [{{r[0-9]+}}]!
|
;CHECK: vst1.8 {{{d[0-9]+}}}, [{{r[0-9]+}}]!
|
||||||
%A = load <4 x i16>** %ptr
|
%A = load <4 x i16>** %ptr
|
||||||
store <4 x i16> %val, <4 x i16>* %A, align 1
|
store <4 x i16> %val, <4 x i16>* %A, align 1
|
||||||
%inc = getelementptr <4 x i16>* %A, i34 1
|
%inc = getelementptr <4 x i16>* %A, i34 1
|
||||||
@ -49,7 +49,7 @@ define void @store_v2i32(<2 x i32>** %ptr, <2 x i32> %val) {
|
|||||||
|
|
||||||
define void @store_v2i32_update(<2 x i32>** %ptr, <2 x i32> %val) {
|
define void @store_v2i32_update(<2 x i32>** %ptr, <2 x i32> %val) {
|
||||||
;CHECK-LABEL: store_v2i32_update:
|
;CHECK-LABEL: store_v2i32_update:
|
||||||
;CHECK: vst1.32 {{{d[0-9]+}}}, [{{r[0-9]+}}]!
|
;CHECK: vst1.8 {{{d[0-9]+}}}, [{{r[0-9]+}}]!
|
||||||
%A = load <2 x i32>** %ptr
|
%A = load <2 x i32>** %ptr
|
||||||
store <2 x i32> %val, <2 x i32>* %A, align 1
|
store <2 x i32> %val, <2 x i32>* %A, align 1
|
||||||
%inc = getelementptr <2 x i32>* %A, i32 1
|
%inc = getelementptr <2 x i32>* %A, i32 1
|
||||||
@ -67,7 +67,7 @@ define void @store_v2f32(<2 x float>** %ptr, <2 x float> %val) {
|
|||||||
|
|
||||||
define void @store_v2f32_update(<2 x float>** %ptr, <2 x float> %val) {
|
define void @store_v2f32_update(<2 x float>** %ptr, <2 x float> %val) {
|
||||||
;CHECK-LABEL: store_v2f32_update:
|
;CHECK-LABEL: store_v2f32_update:
|
||||||
;CHECK: vst1.32 {{{d[0-9]+}}}, [{{r[0-9]+}}]!
|
;CHECK: vst1.8 {{{d[0-9]+}}}, [{{r[0-9]+}}]!
|
||||||
%A = load <2 x float>** %ptr
|
%A = load <2 x float>** %ptr
|
||||||
store <2 x float> %val, <2 x float>* %A, align 1
|
store <2 x float> %val, <2 x float>* %A, align 1
|
||||||
%inc = getelementptr <2 x float>* %A, i32 1
|
%inc = getelementptr <2 x float>* %A, i32 1
|
||||||
@ -85,7 +85,7 @@ define void @store_v1i64(<1 x i64>** %ptr, <1 x i64> %val) {
|
|||||||
|
|
||||||
define void @store_v1i64_update(<1 x i64>** %ptr, <1 x i64> %val) {
|
define void @store_v1i64_update(<1 x i64>** %ptr, <1 x i64> %val) {
|
||||||
;CHECK-LABEL: store_v1i64_update:
|
;CHECK-LABEL: store_v1i64_update:
|
||||||
;CHECK: vst1.64 {{{d[0-9]+}}}, [{{r[0-9]+}}]!
|
;CHECK: vst1.8 {{{d[0-9]+}}}, [{{r[0-9]+}}]!
|
||||||
%A = load <1 x i64>** %ptr
|
%A = load <1 x i64>** %ptr
|
||||||
store <1 x i64> %val, <1 x i64>* %A, align 1
|
store <1 x i64> %val, <1 x i64>* %A, align 1
|
||||||
%inc = getelementptr <1 x i64>* %A, i31 1
|
%inc = getelementptr <1 x i64>* %A, i31 1
|
||||||
@ -121,7 +121,7 @@ define void @store_v8i16(<8 x i16>** %ptr, <8 x i16> %val) {
|
|||||||
|
|
||||||
define void @store_v8i16_update(<8 x i16>** %ptr, <8 x i16> %val) {
|
define void @store_v8i16_update(<8 x i16>** %ptr, <8 x i16> %val) {
|
||||||
;CHECK-LABEL: store_v8i16_update:
|
;CHECK-LABEL: store_v8i16_update:
|
||||||
;CHECK: vst1.16 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]!
|
;CHECK: vst1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]!
|
||||||
%A = load <8 x i16>** %ptr
|
%A = load <8 x i16>** %ptr
|
||||||
store <8 x i16> %val, <8 x i16>* %A, align 1
|
store <8 x i16> %val, <8 x i16>* %A, align 1
|
||||||
%inc = getelementptr <8 x i16>* %A, i38 1
|
%inc = getelementptr <8 x i16>* %A, i38 1
|
||||||
@ -139,7 +139,7 @@ define void @store_v4i32(<4 x i32>** %ptr, <4 x i32> %val) {
|
|||||||
|
|
||||||
define void @store_v4i32_update(<4 x i32>** %ptr, <4 x i32> %val) {
|
define void @store_v4i32_update(<4 x i32>** %ptr, <4 x i32> %val) {
|
||||||
;CHECK-LABEL: store_v4i32_update:
|
;CHECK-LABEL: store_v4i32_update:
|
||||||
;CHECK: vst1.32 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]!
|
;CHECK: vst1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]!
|
||||||
%A = load <4 x i32>** %ptr
|
%A = load <4 x i32>** %ptr
|
||||||
store <4 x i32> %val, <4 x i32>* %A, align 1
|
store <4 x i32> %val, <4 x i32>* %A, align 1
|
||||||
%inc = getelementptr <4 x i32>* %A, i34 1
|
%inc = getelementptr <4 x i32>* %A, i34 1
|
||||||
@ -157,7 +157,7 @@ define void @store_v4f32(<4 x float>** %ptr, <4 x float> %val) {
|
|||||||
|
|
||||||
define void @store_v4f32_update(<4 x float>** %ptr, <4 x float> %val) {
|
define void @store_v4f32_update(<4 x float>** %ptr, <4 x float> %val) {
|
||||||
;CHECK-LABEL: store_v4f32_update:
|
;CHECK-LABEL: store_v4f32_update:
|
||||||
;CHECK: vst1.32 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]!
|
;CHECK: vst1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]!
|
||||||
%A = load <4 x float>** %ptr
|
%A = load <4 x float>** %ptr
|
||||||
store <4 x float> %val, <4 x float>* %A, align 1
|
store <4 x float> %val, <4 x float>* %A, align 1
|
||||||
%inc = getelementptr <4 x float>* %A, i34 1
|
%inc = getelementptr <4 x float>* %A, i34 1
|
||||||
@ -175,7 +175,7 @@ define void @store_v2i64(<2 x i64>** %ptr, <2 x i64> %val) {
|
|||||||
|
|
||||||
define void @store_v2i64_update(<2 x i64>** %ptr, <2 x i64> %val) {
|
define void @store_v2i64_update(<2 x i64>** %ptr, <2 x i64> %val) {
|
||||||
;CHECK-LABEL: store_v2i64_update:
|
;CHECK-LABEL: store_v2i64_update:
|
||||||
;CHECK: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]!
|
;CHECK: vst1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]!
|
||||||
%A = load <2 x i64>** %ptr
|
%A = load <2 x i64>** %ptr
|
||||||
store <2 x i64> %val, <2 x i64>* %A, align 1
|
store <2 x i64> %val, <2 x i64>* %A, align 1
|
||||||
%inc = getelementptr <2 x i64>* %A, i32 1
|
%inc = getelementptr <2 x i64>* %A, i32 1
|
||||||
@ -183,6 +183,46 @@ define void @store_v2i64_update(<2 x i64>** %ptr, <2 x i64> %val) {
|
|||||||
ret void
|
ret void
|
||||||
}
|
}
|
||||||
|
|
||||||
|
define void @store_v2i64_update_aligned2(<2 x i64>** %ptr, <2 x i64> %val) {
|
||||||
|
;CHECK-LABEL: store_v2i64_update_aligned2:
|
||||||
|
;CHECK: vst1.16 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]!
|
||||||
|
%A = load <2 x i64>** %ptr
|
||||||
|
store <2 x i64> %val, <2 x i64>* %A, align 2
|
||||||
|
%inc = getelementptr <2 x i64>* %A, i32 1
|
||||||
|
store <2 x i64>* %inc, <2 x i64>** %ptr
|
||||||
|
ret void
|
||||||
|
}
|
||||||
|
|
||||||
|
define void @store_v2i64_update_aligned4(<2 x i64>** %ptr, <2 x i64> %val) {
|
||||||
|
;CHECK-LABEL: store_v2i64_update_aligned4:
|
||||||
|
;CHECK: vst1.32 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]!
|
||||||
|
%A = load <2 x i64>** %ptr
|
||||||
|
store <2 x i64> %val, <2 x i64>* %A, align 4
|
||||||
|
%inc = getelementptr <2 x i64>* %A, i32 1
|
||||||
|
store <2 x i64>* %inc, <2 x i64>** %ptr
|
||||||
|
ret void
|
||||||
|
}
|
||||||
|
|
||||||
|
define void @store_v2i64_update_aligned8(<2 x i64>** %ptr, <2 x i64> %val) {
|
||||||
|
;CHECK-LABEL: store_v2i64_update_aligned8:
|
||||||
|
;CHECK: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}:64]!
|
||||||
|
%A = load <2 x i64>** %ptr
|
||||||
|
store <2 x i64> %val, <2 x i64>* %A, align 8
|
||||||
|
%inc = getelementptr <2 x i64>* %A, i32 1
|
||||||
|
store <2 x i64>* %inc, <2 x i64>** %ptr
|
||||||
|
ret void
|
||||||
|
}
|
||||||
|
|
||||||
|
define void @store_v2i64_update_aligned16(<2 x i64>** %ptr, <2 x i64> %val) {
|
||||||
|
;CHECK-LABEL: store_v2i64_update_aligned16:
|
||||||
|
;CHECK: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}:128]!
|
||||||
|
%A = load <2 x i64>** %ptr
|
||||||
|
store <2 x i64> %val, <2 x i64>* %A, align 16
|
||||||
|
%inc = getelementptr <2 x i64>* %A, i32 1
|
||||||
|
store <2 x i64>* %inc, <2 x i64>** %ptr
|
||||||
|
ret void
|
||||||
|
}
|
||||||
|
|
||||||
define void @truncstore_v4i32tov4i8(<4 x i8>** %ptr, <4 x i32> %val) {
|
define void @truncstore_v4i32tov4i8(<4 x i8>** %ptr, <4 x i32> %val) {
|
||||||
;CHECK-LABEL: truncstore_v4i32tov4i8:
|
;CHECK-LABEL: truncstore_v4i32tov4i8:
|
||||||
;CHECK: ldr.w r9, [sp]
|
;CHECK: ldr.w r9, [sp]
|
||||||
@ -191,10 +231,10 @@ define void @truncstore_v4i32tov4i8(<4 x i8>** %ptr, <4 x i32> %val) {
|
|||||||
;CHECK: vmovn.i32 [[VECLO:d[0-9]+]], {{q[0-9]+}}
|
;CHECK: vmovn.i32 [[VECLO:d[0-9]+]], {{q[0-9]+}}
|
||||||
;CHECK: vuzp.8 [[VECLO]], {{d[0-9]+}}
|
;CHECK: vuzp.8 [[VECLO]], {{d[0-9]+}}
|
||||||
;CHECK: ldr r[[PTRREG:[0-9]+]], [r0]
|
;CHECK: ldr r[[PTRREG:[0-9]+]], [r0]
|
||||||
;CHECK: vst1.32 {[[VECLO]][0]}, [r[[PTRREG]]]
|
;CHECK: vst1.32 {[[VECLO]][0]}, [r[[PTRREG]]:32]
|
||||||
%A = load <4 x i8>** %ptr
|
%A = load <4 x i8>** %ptr
|
||||||
%trunc = trunc <4 x i32> %val to <4 x i8>
|
%trunc = trunc <4 x i32> %val to <4 x i8>
|
||||||
store <4 x i8> %trunc, <4 x i8>* %A, align 1
|
store <4 x i8> %trunc, <4 x i8>* %A, align 4
|
||||||
ret void
|
ret void
|
||||||
}
|
}
|
||||||
|
|
||||||
|
Loading…
Reference in New Issue
Block a user