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Fix PostRA antidependence breaker.
Avoid using the same register for two def operands or and earlyclobber def and use operand. This fixes PR8986 and improves on the prior fix for rdar://problem/8959122. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125089 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -325,17 +325,55 @@ void CriticalAntiDepBreaker::ScanInstruction(MachineInstr *MI,
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}
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}
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// Check all machine instructions that define the antidependent register.
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// Return true if any of these instructions define the new register.
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// Check all machine operands that reference the antidependent register and must
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// be replaced by NewReg. Return true if any of their parent instructions may
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// clobber the new register.
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//
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// Note: AntiDepReg may be referenced by a two-address instruction such that
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// it's use operand is tied to a def operand. We guard against the case in which
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// the two-address instruction also defines NewReg, as may happen with
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// pre/postincrement loads. In this case, both the use and def operands are in
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// RegRefs because the def is inserted by PrescanInstruction and not erased
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// during ScanInstruction. So checking for an instructions with definitions of
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// both NewReg and AntiDepReg covers it.
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bool
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CriticalAntiDepBreaker::isNewRegModifiedByRefs(RegRefIter RegRefBegin,
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CriticalAntiDepBreaker::isNewRegClobberedByRefs(RegRefIter RegRefBegin,
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RegRefIter RegRefEnd,
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unsigned NewReg)
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{
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for (RegRefIter I = RegRefBegin; I != RegRefEnd; ++I ) {
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MachineOperand *MO = I->second;
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if (MO->getParent()->modifiesRegister(NewReg, TRI))
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MachineOperand *RefOper = I->second;
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// Don't allow the instruction defining AntiDepReg to earlyclobber its
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// operands, in case they may be assigned to NewReg. In this case antidep
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// breaking must fail, but it's too rare to bother optimizing.
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if (RefOper->isDef() && RefOper->isEarlyClobber())
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return true;
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// Handle cases in which this instructions defines NewReg.
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MachineInstr *MI = RefOper->getParent();
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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const MachineOperand &CheckOper = MI->getOperand(i);
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if (!CheckOper.isReg() || !CheckOper.isDef() ||
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CheckOper.getReg() != NewReg)
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continue;
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// Don't allow the instruction to define NewReg and AntiDepReg.
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// When AntiDepReg is renamed it will be an illegal op.
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if (RefOper->isDef())
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return true;
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// Don't allow an instruction using AntiDepReg to be earlyclobbered by
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// NewReg
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if (CheckOper.isEarlyClobber())
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return true;
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// Don't allow inline asm to define NewReg at all. Who know what it's
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// doing with it.
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if (MI->isInlineAsm())
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return true;
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}
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}
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return false;
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}
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@ -361,7 +399,7 @@ CriticalAntiDepBreaker::findSuitableFreeRegister(RegRefIter RegRefBegin,
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// If any instructions that define AntiDepReg also define the NewReg, it's
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// not suitable. For example, Instruction with multiple definitions can
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// result in this condition.
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if (isNewRegModifiedByRefs(RegRefBegin, RegRefEnd, NewReg)) continue;
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if (isNewRegClobberedByRefs(RegRefBegin, RegRefEnd, NewReg)) continue;
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// If NewReg is dead and NewReg's most recent def is not before
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// AntiDepReg's kill, it's safe to replace AntiDepReg with NewReg.
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assert(((KillIndices[AntiDepReg] == ~0u) != (DefIndices[AntiDepReg] == ~0u))
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@ -92,7 +92,7 @@ class TargetRegisterInfo;
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private:
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void PrescanInstruction(MachineInstr *MI);
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void ScanInstruction(MachineInstr *MI, unsigned Count);
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bool isNewRegModifiedByRefs(RegRefIter RegRefBegin,
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bool isNewRegClobberedByRefs(RegRefIter RegRefBegin,
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RegRefIter RegRefEnd,
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unsigned NewReg);
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unsigned findSuitableFreeRegister(RegRefIter RegRefBegin,
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