mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-08 18:30:04 +00:00
[mips][msa] Added tests for and.v, bmnz.v, bmz.v, bsel.v, nor.v, or.v, xor.v when non-byte vectors are used.
Note that all of these tests use ld.b and st.b for the loads and stores regardless of the data size. This is because the definition of bitcast is equivalent to a store/load sequence and DAG combiner accordingly folds bitcasts to/from v16i8 into the load/store nodes to product load/store nodes with type v16i8. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189333 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Daniel Sanders
parent
62f61bf907
commit
bc4e0586bd
@ -1,4 +1,5 @@
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; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
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; RUN: llc -march=mips -mattr=+msa < %s | FileCheck -check-prefix=ANYENDIAN %s
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; RUN: llc -march=mipsel -mattr=+msa < %s | FileCheck -check-prefix=ANYENDIAN %s
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;
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; Test the MSA intrinsics that are encoded with the VEC instruction format.
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@ -18,12 +19,81 @@ entry:
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ret void
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}
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; CHECK: llvm_mips_and_v_b_test:
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; CHECK: ld.b
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; CHECK: ld.b
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; CHECK: and.v
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; CHECK: st.b
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; CHECK: .size llvm_mips_and_v_b_test
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; ANYENDIAN: llvm_mips_and_v_b_test:
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; ANYENDIAN: ld.b
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; ANYENDIAN: ld.b
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; ANYENDIAN: and.v
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; ANYENDIAN: st.b
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; ANYENDIAN: .size llvm_mips_and_v_b_test
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;
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@llvm_mips_and_v_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
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@llvm_mips_and_v_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16
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@llvm_mips_and_v_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16
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define void @llvm_mips_and_v_h_test() nounwind {
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entry:
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%0 = load <8 x i16>* @llvm_mips_and_v_h_ARG1
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%1 = load <8 x i16>* @llvm_mips_and_v_h_ARG2
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%2 = bitcast <8 x i16> %0 to <16 x i8>
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%3 = bitcast <8 x i16> %1 to <16 x i8>
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%4 = tail call <16 x i8> @llvm.mips.and.v(<16 x i8> %2, <16 x i8> %3)
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%5 = bitcast <16 x i8> %4 to <8 x i16>
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store <8 x i16> %5, <8 x i16>* @llvm_mips_and_v_h_RES
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ret void
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}
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; ANYENDIAN: llvm_mips_and_v_h_test:
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; ANYENDIAN: ld.b
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; ANYENDIAN: ld.b
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; ANYENDIAN: and.v
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; ANYENDIAN: st.b
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; ANYENDIAN: .size llvm_mips_and_v_h_test
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;
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@llvm_mips_and_v_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
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@llvm_mips_and_v_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16
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@llvm_mips_and_v_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
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define void @llvm_mips_and_v_w_test() nounwind {
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entry:
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%0 = load <4 x i32>* @llvm_mips_and_v_w_ARG1
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%1 = load <4 x i32>* @llvm_mips_and_v_w_ARG2
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%2 = bitcast <4 x i32> %0 to <16 x i8>
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%3 = bitcast <4 x i32> %1 to <16 x i8>
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%4 = tail call <16 x i8> @llvm.mips.and.v(<16 x i8> %2, <16 x i8> %3)
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%5 = bitcast <16 x i8> %4 to <4 x i32>
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store <4 x i32> %5, <4 x i32>* @llvm_mips_and_v_w_RES
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ret void
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}
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; ANYENDIAN: llvm_mips_and_v_w_test:
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; ANYENDIAN: ld.b
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; ANYENDIAN: ld.b
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; ANYENDIAN: and.v
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; ANYENDIAN: st.b
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; ANYENDIAN: .size llvm_mips_and_v_w_test
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;
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@llvm_mips_and_v_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16
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@llvm_mips_and_v_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 16
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@llvm_mips_and_v_d_RES = global <2 x i64> <i64 0, i64 0>, align 16
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define void @llvm_mips_and_v_d_test() nounwind {
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entry:
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%0 = load <2 x i64>* @llvm_mips_and_v_d_ARG1
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%1 = load <2 x i64>* @llvm_mips_and_v_d_ARG2
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%2 = bitcast <2 x i64> %0 to <16 x i8>
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%3 = bitcast <2 x i64> %1 to <16 x i8>
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%4 = tail call <16 x i8> @llvm.mips.and.v(<16 x i8> %2, <16 x i8> %3)
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%5 = bitcast <16 x i8> %4 to <2 x i64>
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store <2 x i64> %5, <2 x i64>* @llvm_mips_and_v_d_RES
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ret void
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}
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; ANYENDIAN: llvm_mips_and_v_d_test:
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; ANYENDIAN: ld.b
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; ANYENDIAN: ld.b
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; ANYENDIAN: and.v
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; ANYENDIAN: st.b
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; ANYENDIAN: .size llvm_mips_and_v_d_test
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;
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@llvm_mips_bmnz_v_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
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@llvm_mips_bmnz_v_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16
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@ -41,12 +111,81 @@ entry:
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ret void
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}
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; CHECK: llvm_mips_bmnz_v_b_test:
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; CHECK: ld.b
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; CHECK: ld.b
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; CHECK: bmnz.v
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; CHECK: st.b
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; CHECK: .size llvm_mips_bmnz_v_b_test
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; ANYENDIAN: llvm_mips_bmnz_v_b_test:
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; ANYENDIAN: ld.b
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; ANYENDIAN: ld.b
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; ANYENDIAN: bmnz.v
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; ANYENDIAN: st.b
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; ANYENDIAN: .size llvm_mips_bmnz_v_b_test
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;
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@llvm_mips_bmnz_v_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
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@llvm_mips_bmnz_v_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16
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@llvm_mips_bmnz_v_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16
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define void @llvm_mips_bmnz_v_h_test() nounwind {
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entry:
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%0 = load <8 x i16>* @llvm_mips_bmnz_v_h_ARG1
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%1 = load <8 x i16>* @llvm_mips_bmnz_v_h_ARG2
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%2 = bitcast <8 x i16> %0 to <16 x i8>
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%3 = bitcast <8 x i16> %1 to <16 x i8>
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%4 = tail call <16 x i8> @llvm.mips.bmnz.v(<16 x i8> %2, <16 x i8> %3)
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%5 = bitcast <16 x i8> %4 to <8 x i16>
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store <8 x i16> %5, <8 x i16>* @llvm_mips_bmnz_v_h_RES
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ret void
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}
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; ANYENDIAN: llvm_mips_bmnz_v_h_test:
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; ANYENDIAN: ld.b
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; ANYENDIAN: ld.b
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; ANYENDIAN: bmnz.v
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; ANYENDIAN: st.b
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; ANYENDIAN: .size llvm_mips_bmnz_v_h_test
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;
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@llvm_mips_bmnz_v_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
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@llvm_mips_bmnz_v_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16
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@llvm_mips_bmnz_v_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
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define void @llvm_mips_bmnz_v_w_test() nounwind {
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entry:
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%0 = load <4 x i32>* @llvm_mips_bmnz_v_w_ARG1
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%1 = load <4 x i32>* @llvm_mips_bmnz_v_w_ARG2
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%2 = bitcast <4 x i32> %0 to <16 x i8>
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%3 = bitcast <4 x i32> %1 to <16 x i8>
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%4 = tail call <16 x i8> @llvm.mips.bmnz.v(<16 x i8> %2, <16 x i8> %3)
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%5 = bitcast <16 x i8> %4 to <4 x i32>
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store <4 x i32> %5, <4 x i32>* @llvm_mips_bmnz_v_w_RES
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ret void
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}
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; ANYENDIAN: llvm_mips_bmnz_v_w_test:
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; ANYENDIAN: ld.b
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; ANYENDIAN: ld.b
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; ANYENDIAN: bmnz.v
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; ANYENDIAN: st.b
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; ANYENDIAN: .size llvm_mips_bmnz_v_w_test
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;
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@llvm_mips_bmnz_v_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16
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@llvm_mips_bmnz_v_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 16
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@llvm_mips_bmnz_v_d_RES = global <2 x i64> <i64 0, i64 0>, align 16
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define void @llvm_mips_bmnz_v_d_test() nounwind {
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entry:
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%0 = load <2 x i64>* @llvm_mips_bmnz_v_d_ARG1
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%1 = load <2 x i64>* @llvm_mips_bmnz_v_d_ARG2
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%2 = bitcast <2 x i64> %0 to <16 x i8>
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%3 = bitcast <2 x i64> %1 to <16 x i8>
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%4 = tail call <16 x i8> @llvm.mips.bmnz.v(<16 x i8> %2, <16 x i8> %3)
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%5 = bitcast <16 x i8> %4 to <2 x i64>
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store <2 x i64> %5, <2 x i64>* @llvm_mips_bmnz_v_d_RES
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ret void
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}
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; ANYENDIAN: llvm_mips_bmnz_v_d_test:
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; ANYENDIAN: ld.b
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; ANYENDIAN: ld.b
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; ANYENDIAN: bmnz.v
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; ANYENDIAN: st.b
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; ANYENDIAN: .size llvm_mips_bmnz_v_d_test
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;
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@llvm_mips_bmz_v_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
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@llvm_mips_bmz_v_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16
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@ -64,17 +203,82 @@ entry:
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ret void
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}
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; CHECK: llvm_mips_bmz_v_b_test:
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; CHECK: ld.b
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; CHECK: ld.b
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; CHECK: bmz.v
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; CHECK: st.b
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; CHECK: .size llvm_mips_bmz_v_b_test
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; ANYENDIAN: llvm_mips_bmz_v_b_test:
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; ANYENDIAN: ld.b
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; ANYENDIAN: ld.b
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; ANYENDIAN: bmz.v
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; ANYENDIAN: st.b
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; ANYENDIAN: .size llvm_mips_bmz_v_b_test
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;
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@llvm_mips_bmz_v_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
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@llvm_mips_bmz_v_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16
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@llvm_mips_bmz_v_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16
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define void @llvm_mips_bmz_v_h_test() nounwind {
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entry:
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%0 = load <8 x i16>* @llvm_mips_bmz_v_h_ARG1
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%1 = load <8 x i16>* @llvm_mips_bmz_v_h_ARG2
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%2 = bitcast <8 x i16> %0 to <16 x i8>
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%3 = bitcast <8 x i16> %1 to <16 x i8>
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%4 = tail call <16 x i8> @llvm.mips.bmz.v(<16 x i8> %2, <16 x i8> %3)
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%5 = bitcast <16 x i8> %4 to <8 x i16>
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store <8 x i16> %5, <8 x i16>* @llvm_mips_bmz_v_h_RES
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ret void
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}
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; ANYENDIAN: llvm_mips_bmz_v_h_test:
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; ANYENDIAN: ld.b
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; ANYENDIAN: ld.b
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; ANYENDIAN: bmz.v
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; ANYENDIAN: st.b
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; ANYENDIAN: .size llvm_mips_bmz_v_h_test
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;
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@llvm_mips_bmz_v_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
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@llvm_mips_bmz_v_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16
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@llvm_mips_bmz_v_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
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define void @llvm_mips_bmz_v_w_test() nounwind {
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entry:
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%0 = load <4 x i32>* @llvm_mips_bmz_v_w_ARG1
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%1 = load <4 x i32>* @llvm_mips_bmz_v_w_ARG2
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%2 = bitcast <4 x i32> %0 to <16 x i8>
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%3 = bitcast <4 x i32> %1 to <16 x i8>
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%4 = tail call <16 x i8> @llvm.mips.bmz.v(<16 x i8> %2, <16 x i8> %3)
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%5 = bitcast <16 x i8> %4 to <4 x i32>
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store <4 x i32> %5, <4 x i32>* @llvm_mips_bmz_v_w_RES
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ret void
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}
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; ANYENDIAN: llvm_mips_bmz_v_w_test:
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; ANYENDIAN: ld.b
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; ANYENDIAN: ld.b
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; ANYENDIAN: bmz.v
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; ANYENDIAN: st.b
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; ANYENDIAN: .size llvm_mips_bmz_v_w_test
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;
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@llvm_mips_bmz_v_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16
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@llvm_mips_bmz_v_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 16
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@llvm_mips_bmz_v_d_RES = global <2 x i64> <i64 0, i64 0>, align 16
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define void @llvm_mips_bmz_v_d_test() nounwind {
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entry:
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%0 = load <2 x i64>* @llvm_mips_bmz_v_d_ARG1
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%1 = load <2 x i64>* @llvm_mips_bmz_v_d_ARG2
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%2 = bitcast <2 x i64> %0 to <16 x i8>
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%3 = bitcast <2 x i64> %1 to <16 x i8>
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%4 = tail call <16 x i8> @llvm.mips.bmz.v(<16 x i8> %2, <16 x i8> %3)
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%5 = bitcast <16 x i8> %4 to <2 x i64>
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store <2 x i64> %5, <2 x i64>* @llvm_mips_bmz_v_d_RES
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ret void
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}
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; ANYENDIAN: llvm_mips_bmz_v_d_test:
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; ANYENDIAN: ld.b
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; ANYENDIAN: ld.b
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; ANYENDIAN: bmz.v
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; ANYENDIAN: st.b
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; ANYENDIAN: .size llvm_mips_bmz_v_d_test
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;
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@llvm_mips_bsel_v_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
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@llvm_mips_bsel_v_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16
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@llvm_mips_bsel_v_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
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@ -91,12 +295,81 @@ entry:
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ret void
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}
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; CHECK: llvm_mips_bsel_v_b_test:
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; CHECK: ld.b
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; CHECK: ld.b
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; CHECK: bsel.v
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; CHECK: st.b
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; CHECK: .size llvm_mips_bsel_v_b_test
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; ANYENDIAN: llvm_mips_bsel_v_b_test:
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; ANYENDIAN: ld.b
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; ANYENDIAN: ld.b
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; ANYENDIAN: bsel.v
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; ANYENDIAN: st.b
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; ANYENDIAN: .size llvm_mips_bsel_v_b_test
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;
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@llvm_mips_bsel_v_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
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@llvm_mips_bsel_v_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16
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@llvm_mips_bsel_v_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16
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define void @llvm_mips_bsel_v_h_test() nounwind {
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entry:
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%0 = load <8 x i16>* @llvm_mips_bsel_v_h_ARG1
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||||
%1 = load <8 x i16>* @llvm_mips_bsel_v_h_ARG2
|
||||
%2 = bitcast <8 x i16> %0 to <16 x i8>
|
||||
%3 = bitcast <8 x i16> %1 to <16 x i8>
|
||||
%4 = tail call <16 x i8> @llvm.mips.bsel.v(<16 x i8> %2, <16 x i8> %3)
|
||||
%5 = bitcast <16 x i8> %4 to <8 x i16>
|
||||
store <8 x i16> %5, <8 x i16>* @llvm_mips_bsel_v_h_RES
|
||||
ret void
|
||||
}
|
||||
|
||||
; ANYENDIAN: llvm_mips_bsel_v_h_test:
|
||||
; ANYENDIAN: ld.b
|
||||
; ANYENDIAN: ld.b
|
||||
; ANYENDIAN: bsel.v
|
||||
; ANYENDIAN: st.b
|
||||
; ANYENDIAN: .size llvm_mips_bsel_v_h_test
|
||||
;
|
||||
@llvm_mips_bsel_v_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
|
||||
@llvm_mips_bsel_v_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16
|
||||
@llvm_mips_bsel_v_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
|
||||
|
||||
define void @llvm_mips_bsel_v_w_test() nounwind {
|
||||
entry:
|
||||
%0 = load <4 x i32>* @llvm_mips_bsel_v_w_ARG1
|
||||
%1 = load <4 x i32>* @llvm_mips_bsel_v_w_ARG2
|
||||
%2 = bitcast <4 x i32> %0 to <16 x i8>
|
||||
%3 = bitcast <4 x i32> %1 to <16 x i8>
|
||||
%4 = tail call <16 x i8> @llvm.mips.bsel.v(<16 x i8> %2, <16 x i8> %3)
|
||||
%5 = bitcast <16 x i8> %4 to <4 x i32>
|
||||
store <4 x i32> %5, <4 x i32>* @llvm_mips_bsel_v_w_RES
|
||||
ret void
|
||||
}
|
||||
|
||||
; ANYENDIAN: llvm_mips_bsel_v_w_test:
|
||||
; ANYENDIAN: ld.b
|
||||
; ANYENDIAN: ld.b
|
||||
; ANYENDIAN: bsel.v
|
||||
; ANYENDIAN: st.b
|
||||
; ANYENDIAN: .size llvm_mips_bsel_v_w_test
|
||||
;
|
||||
@llvm_mips_bsel_v_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16
|
||||
@llvm_mips_bsel_v_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 16
|
||||
@llvm_mips_bsel_v_d_RES = global <2 x i64> <i64 0, i64 0>, align 16
|
||||
|
||||
define void @llvm_mips_bsel_v_d_test() nounwind {
|
||||
entry:
|
||||
%0 = load <2 x i64>* @llvm_mips_bsel_v_d_ARG1
|
||||
%1 = load <2 x i64>* @llvm_mips_bsel_v_d_ARG2
|
||||
%2 = bitcast <2 x i64> %0 to <16 x i8>
|
||||
%3 = bitcast <2 x i64> %1 to <16 x i8>
|
||||
%4 = tail call <16 x i8> @llvm.mips.bsel.v(<16 x i8> %2, <16 x i8> %3)
|
||||
%5 = bitcast <16 x i8> %4 to <2 x i64>
|
||||
store <2 x i64> %5, <2 x i64>* @llvm_mips_bsel_v_d_RES
|
||||
ret void
|
||||
}
|
||||
|
||||
; ANYENDIAN: llvm_mips_bsel_v_d_test:
|
||||
; ANYENDIAN: ld.b
|
||||
; ANYENDIAN: ld.b
|
||||
; ANYENDIAN: bsel.v
|
||||
; ANYENDIAN: st.b
|
||||
; ANYENDIAN: .size llvm_mips_bsel_v_d_test
|
||||
;
|
||||
@llvm_mips_nor_v_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
|
||||
@llvm_mips_nor_v_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16
|
||||
@ -114,12 +387,81 @@ entry:
|
||||
ret void
|
||||
}
|
||||
|
||||
; CHECK: llvm_mips_nor_v_b_test:
|
||||
; CHECK: ld.b
|
||||
; CHECK: ld.b
|
||||
; CHECK: nor.v
|
||||
; CHECK: st.b
|
||||
; CHECK: .size llvm_mips_nor_v_b_test
|
||||
; ANYENDIAN: llvm_mips_nor_v_b_test:
|
||||
; ANYENDIAN: ld.b
|
||||
; ANYENDIAN: ld.b
|
||||
; ANYENDIAN: nor.v
|
||||
; ANYENDIAN: st.b
|
||||
; ANYENDIAN: .size llvm_mips_nor_v_b_test
|
||||
;
|
||||
@llvm_mips_nor_v_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
|
||||
@llvm_mips_nor_v_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16
|
||||
@llvm_mips_nor_v_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16
|
||||
|
||||
define void @llvm_mips_nor_v_h_test() nounwind {
|
||||
entry:
|
||||
%0 = load <8 x i16>* @llvm_mips_nor_v_h_ARG1
|
||||
%1 = load <8 x i16>* @llvm_mips_nor_v_h_ARG2
|
||||
%2 = bitcast <8 x i16> %0 to <16 x i8>
|
||||
%3 = bitcast <8 x i16> %1 to <16 x i8>
|
||||
%4 = tail call <16 x i8> @llvm.mips.nor.v(<16 x i8> %2, <16 x i8> %3)
|
||||
%5 = bitcast <16 x i8> %4 to <8 x i16>
|
||||
store <8 x i16> %5, <8 x i16>* @llvm_mips_nor_v_h_RES
|
||||
ret void
|
||||
}
|
||||
|
||||
; ANYENDIAN: llvm_mips_nor_v_h_test:
|
||||
; ANYENDIAN: ld.b
|
||||
; ANYENDIAN: ld.b
|
||||
; ANYENDIAN: nor.v
|
||||
; ANYENDIAN: st.b
|
||||
; ANYENDIAN: .size llvm_mips_nor_v_h_test
|
||||
;
|
||||
@llvm_mips_nor_v_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
|
||||
@llvm_mips_nor_v_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16
|
||||
@llvm_mips_nor_v_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
|
||||
|
||||
define void @llvm_mips_nor_v_w_test() nounwind {
|
||||
entry:
|
||||
%0 = load <4 x i32>* @llvm_mips_nor_v_w_ARG1
|
||||
%1 = load <4 x i32>* @llvm_mips_nor_v_w_ARG2
|
||||
%2 = bitcast <4 x i32> %0 to <16 x i8>
|
||||
%3 = bitcast <4 x i32> %1 to <16 x i8>
|
||||
%4 = tail call <16 x i8> @llvm.mips.nor.v(<16 x i8> %2, <16 x i8> %3)
|
||||
%5 = bitcast <16 x i8> %4 to <4 x i32>
|
||||
store <4 x i32> %5, <4 x i32>* @llvm_mips_nor_v_w_RES
|
||||
ret void
|
||||
}
|
||||
|
||||
; ANYENDIAN: llvm_mips_nor_v_w_test:
|
||||
; ANYENDIAN: ld.b
|
||||
; ANYENDIAN: ld.b
|
||||
; ANYENDIAN: nor.v
|
||||
; ANYENDIAN: st.b
|
||||
; ANYENDIAN: .size llvm_mips_nor_v_w_test
|
||||
;
|
||||
@llvm_mips_nor_v_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16
|
||||
@llvm_mips_nor_v_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 16
|
||||
@llvm_mips_nor_v_d_RES = global <2 x i64> <i64 0, i64 0>, align 16
|
||||
|
||||
define void @llvm_mips_nor_v_d_test() nounwind {
|
||||
entry:
|
||||
%0 = load <2 x i64>* @llvm_mips_nor_v_d_ARG1
|
||||
%1 = load <2 x i64>* @llvm_mips_nor_v_d_ARG2
|
||||
%2 = bitcast <2 x i64> %0 to <16 x i8>
|
||||
%3 = bitcast <2 x i64> %1 to <16 x i8>
|
||||
%4 = tail call <16 x i8> @llvm.mips.nor.v(<16 x i8> %2, <16 x i8> %3)
|
||||
%5 = bitcast <16 x i8> %4 to <2 x i64>
|
||||
store <2 x i64> %5, <2 x i64>* @llvm_mips_nor_v_d_RES
|
||||
ret void
|
||||
}
|
||||
|
||||
; ANYENDIAN: llvm_mips_nor_v_d_test:
|
||||
; ANYENDIAN: ld.b
|
||||
; ANYENDIAN: ld.b
|
||||
; ANYENDIAN: nor.v
|
||||
; ANYENDIAN: st.b
|
||||
; ANYENDIAN: .size llvm_mips_nor_v_d_test
|
||||
;
|
||||
@llvm_mips_or_v_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
|
||||
@llvm_mips_or_v_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16
|
||||
@ -137,12 +479,81 @@ entry:
|
||||
ret void
|
||||
}
|
||||
|
||||
; CHECK: llvm_mips_or_v_b_test:
|
||||
; CHECK: ld.b
|
||||
; CHECK: ld.b
|
||||
; CHECK: or.v
|
||||
; CHECK: st.b
|
||||
; CHECK: .size llvm_mips_or_v_b_test
|
||||
; ANYENDIAN: llvm_mips_or_v_b_test:
|
||||
; ANYENDIAN: ld.b
|
||||
; ANYENDIAN: ld.b
|
||||
; ANYENDIAN: or.v
|
||||
; ANYENDIAN: st.b
|
||||
; ANYENDIAN: .size llvm_mips_or_v_b_test
|
||||
;
|
||||
@llvm_mips_or_v_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
|
||||
@llvm_mips_or_v_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16
|
||||
@llvm_mips_or_v_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16
|
||||
|
||||
define void @llvm_mips_or_v_h_test() nounwind {
|
||||
entry:
|
||||
%0 = load <8 x i16>* @llvm_mips_or_v_h_ARG1
|
||||
%1 = load <8 x i16>* @llvm_mips_or_v_h_ARG2
|
||||
%2 = bitcast <8 x i16> %0 to <16 x i8>
|
||||
%3 = bitcast <8 x i16> %1 to <16 x i8>
|
||||
%4 = tail call <16 x i8> @llvm.mips.or.v(<16 x i8> %2, <16 x i8> %3)
|
||||
%5 = bitcast <16 x i8> %4 to <8 x i16>
|
||||
store <8 x i16> %5, <8 x i16>* @llvm_mips_or_v_h_RES
|
||||
ret void
|
||||
}
|
||||
|
||||
; ANYENDIAN: llvm_mips_or_v_h_test:
|
||||
; ANYENDIAN: ld.b
|
||||
; ANYENDIAN: ld.b
|
||||
; ANYENDIAN: or.v
|
||||
; ANYENDIAN: st.b
|
||||
; ANYENDIAN: .size llvm_mips_or_v_h_test
|
||||
;
|
||||
@llvm_mips_or_v_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
|
||||
@llvm_mips_or_v_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16
|
||||
@llvm_mips_or_v_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
|
||||
|
||||
define void @llvm_mips_or_v_w_test() nounwind {
|
||||
entry:
|
||||
%0 = load <4 x i32>* @llvm_mips_or_v_w_ARG1
|
||||
%1 = load <4 x i32>* @llvm_mips_or_v_w_ARG2
|
||||
%2 = bitcast <4 x i32> %0 to <16 x i8>
|
||||
%3 = bitcast <4 x i32> %1 to <16 x i8>
|
||||
%4 = tail call <16 x i8> @llvm.mips.or.v(<16 x i8> %2, <16 x i8> %3)
|
||||
%5 = bitcast <16 x i8> %4 to <4 x i32>
|
||||
store <4 x i32> %5, <4 x i32>* @llvm_mips_or_v_w_RES
|
||||
ret void
|
||||
}
|
||||
|
||||
; ANYENDIAN: llvm_mips_or_v_w_test:
|
||||
; ANYENDIAN: ld.b
|
||||
; ANYENDIAN: ld.b
|
||||
; ANYENDIAN: or.v
|
||||
; ANYENDIAN: st.b
|
||||
; ANYENDIAN: .size llvm_mips_or_v_w_test
|
||||
;
|
||||
@llvm_mips_or_v_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16
|
||||
@llvm_mips_or_v_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 16
|
||||
@llvm_mips_or_v_d_RES = global <2 x i64> <i64 0, i64 0>, align 16
|
||||
|
||||
define void @llvm_mips_or_v_d_test() nounwind {
|
||||
entry:
|
||||
%0 = load <2 x i64>* @llvm_mips_or_v_d_ARG1
|
||||
%1 = load <2 x i64>* @llvm_mips_or_v_d_ARG2
|
||||
%2 = bitcast <2 x i64> %0 to <16 x i8>
|
||||
%3 = bitcast <2 x i64> %1 to <16 x i8>
|
||||
%4 = tail call <16 x i8> @llvm.mips.or.v(<16 x i8> %2, <16 x i8> %3)
|
||||
%5 = bitcast <16 x i8> %4 to <2 x i64>
|
||||
store <2 x i64> %5, <2 x i64>* @llvm_mips_or_v_d_RES
|
||||
ret void
|
||||
}
|
||||
|
||||
; ANYENDIAN: llvm_mips_or_v_d_test:
|
||||
; ANYENDIAN: ld.b
|
||||
; ANYENDIAN: ld.b
|
||||
; ANYENDIAN: or.v
|
||||
; ANYENDIAN: st.b
|
||||
; ANYENDIAN: .size llvm_mips_or_v_d_test
|
||||
;
|
||||
@llvm_mips_xor_v_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
|
||||
@llvm_mips_xor_v_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16
|
||||
@ -160,12 +571,81 @@ entry:
|
||||
ret void
|
||||
}
|
||||
|
||||
; CHECK: llvm_mips_xor_v_b_test:
|
||||
; CHECK: ld.b
|
||||
; CHECK: ld.b
|
||||
; CHECK: xor.v
|
||||
; CHECK: st.b
|
||||
; CHECK: .size llvm_mips_xor_v_b_test
|
||||
; ANYENDIAN: llvm_mips_xor_v_b_test:
|
||||
; ANYENDIAN: ld.b
|
||||
; ANYENDIAN: ld.b
|
||||
; ANYENDIAN: xor.v
|
||||
; ANYENDIAN: st.b
|
||||
; ANYENDIAN: .size llvm_mips_xor_v_b_test
|
||||
;
|
||||
@llvm_mips_xor_v_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
|
||||
@llvm_mips_xor_v_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16
|
||||
@llvm_mips_xor_v_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16
|
||||
|
||||
define void @llvm_mips_xor_v_h_test() nounwind {
|
||||
entry:
|
||||
%0 = load <8 x i16>* @llvm_mips_xor_v_h_ARG1
|
||||
%1 = load <8 x i16>* @llvm_mips_xor_v_h_ARG2
|
||||
%2 = bitcast <8 x i16> %0 to <16 x i8>
|
||||
%3 = bitcast <8 x i16> %1 to <16 x i8>
|
||||
%4 = tail call <16 x i8> @llvm.mips.xor.v(<16 x i8> %2, <16 x i8> %3)
|
||||
%5 = bitcast <16 x i8> %4 to <8 x i16>
|
||||
store <8 x i16> %5, <8 x i16>* @llvm_mips_xor_v_h_RES
|
||||
ret void
|
||||
}
|
||||
|
||||
; ANYENDIAN: llvm_mips_xor_v_h_test:
|
||||
; ANYENDIAN: ld.b
|
||||
; ANYENDIAN: ld.b
|
||||
; ANYENDIAN: xor.v
|
||||
; ANYENDIAN: st.b
|
||||
; ANYENDIAN: .size llvm_mips_xor_v_h_test
|
||||
;
|
||||
@llvm_mips_xor_v_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
|
||||
@llvm_mips_xor_v_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16
|
||||
@llvm_mips_xor_v_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
|
||||
|
||||
define void @llvm_mips_xor_v_w_test() nounwind {
|
||||
entry:
|
||||
%0 = load <4 x i32>* @llvm_mips_xor_v_w_ARG1
|
||||
%1 = load <4 x i32>* @llvm_mips_xor_v_w_ARG2
|
||||
%2 = bitcast <4 x i32> %0 to <16 x i8>
|
||||
%3 = bitcast <4 x i32> %1 to <16 x i8>
|
||||
%4 = tail call <16 x i8> @llvm.mips.xor.v(<16 x i8> %2, <16 x i8> %3)
|
||||
%5 = bitcast <16 x i8> %4 to <4 x i32>
|
||||
store <4 x i32> %5, <4 x i32>* @llvm_mips_xor_v_w_RES
|
||||
ret void
|
||||
}
|
||||
|
||||
; ANYENDIAN: llvm_mips_xor_v_w_test:
|
||||
; ANYENDIAN: ld.b
|
||||
; ANYENDIAN: ld.b
|
||||
; ANYENDIAN: xor.v
|
||||
; ANYENDIAN: st.b
|
||||
; ANYENDIAN: .size llvm_mips_xor_v_w_test
|
||||
;
|
||||
@llvm_mips_xor_v_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16
|
||||
@llvm_mips_xor_v_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 16
|
||||
@llvm_mips_xor_v_d_RES = global <2 x i64> <i64 0, i64 0>, align 16
|
||||
|
||||
define void @llvm_mips_xor_v_d_test() nounwind {
|
||||
entry:
|
||||
%0 = load <2 x i64>* @llvm_mips_xor_v_d_ARG1
|
||||
%1 = load <2 x i64>* @llvm_mips_xor_v_d_ARG2
|
||||
%2 = bitcast <2 x i64> %0 to <16 x i8>
|
||||
%3 = bitcast <2 x i64> %1 to <16 x i8>
|
||||
%4 = tail call <16 x i8> @llvm.mips.xor.v(<16 x i8> %2, <16 x i8> %3)
|
||||
%5 = bitcast <16 x i8> %4 to <2 x i64>
|
||||
store <2 x i64> %5, <2 x i64>* @llvm_mips_xor_v_d_RES
|
||||
ret void
|
||||
}
|
||||
|
||||
; ANYENDIAN: llvm_mips_xor_v_d_test:
|
||||
; ANYENDIAN: ld.b
|
||||
; ANYENDIAN: ld.b
|
||||
; ANYENDIAN: xor.v
|
||||
; ANYENDIAN: st.b
|
||||
; ANYENDIAN: .size llvm_mips_xor_v_d_test
|
||||
;
|
||||
declare <16 x i8> @llvm.mips.and.v(<16 x i8>, <16 x i8>) nounwind
|
||||
declare <16 x i8> @llvm.mips.bmnz.v(<16 x i8>, <16 x i8>) nounwind
|
||||
|
||||
Loading…
Reference in New Issue
Block a user