From bc53c04789ba11e241ef9793fc3cae5b2902725b Mon Sep 17 00:00:00 2001 From: Chris Lattner Date: Mon, 4 Feb 2002 05:55:10 +0000 Subject: [PATCH] * Minor cleanups * Reduce number of #includes * Delete blank lines at end of files * Remove blatently misleading qualifiers (how do you have an inlined pure virtual function?) * Remove unnecesary & ignored qualifiers (const int argument vs int argument) * Remove LARGE chunks of "inline" code out to .cpp file * s/unsigned int/unsigned/ git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@1673 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/Target/TargetCacheInfo.h | 35 ++--- include/llvm/Target/TargetRegInfo.h | 108 +++++--------- include/llvm/Target/TargetSchedInfo.h | 202 +++++++------------------- 3 files changed, 96 insertions(+), 249 deletions(-) diff --git a/include/llvm/Target/TargetCacheInfo.h b/include/llvm/Target/TargetCacheInfo.h index 0f81dd1a65b..6514c8b6da8 100644 --- a/include/llvm/Target/TargetCacheInfo.h +++ b/include/llvm/Target/TargetCacheInfo.h @@ -1,30 +1,17 @@ -// $Id$ -*-c++-*- -//*************************************************************************** -// File: -// MachineCacheInfo.h -// -// Purpose: -// Describes properties of the target cache architecture. -//**************************************************************************/ +//===-- llvm/Target/MachineCacheInfo.h ---------------------------*- C++ -*-==// +// +// Describes properties of the target cache architecture. +// +//===----------------------------------------------------------------------===// #ifndef LLVM_TARGET_MACHINECACHEINFO_H #define LLVM_TARGET_MACHINECACHEINFO_H -#include "llvm/Target/TargetMachine.h" #include "Support/DataTypes.h" +class TargetMachine; - -//--------------------------------------------------------------------------- -// class MachineCacheInfo -// -// Purpose: -// Describes properties of the target cache architecture. -//--------------------------------------------------------------------------- - -class MachineCacheInfo : public NonCopyableV { -public: - const TargetMachine& target; - +struct MachineCacheInfo : public NonCopyableV { + const TargetMachine ⌖ protected: unsigned int numLevels; std::vector cacheLineSizes; @@ -32,8 +19,7 @@ protected: std::vector cacheAssoc; public: - /*ctor*/ MachineCacheInfo (const TargetMachine& tgt); - /*dtor*/ virtual ~MachineCacheInfo () {} + MachineCacheInfo(const TargetMachine& tgt); // Default parameters are: // NumLevels = 2 @@ -60,7 +46,4 @@ public: } }; - -//--------------------------------------------------------------------------- - #endif diff --git a/include/llvm/Target/TargetRegInfo.h b/include/llvm/Target/TargetRegInfo.h index b2fa0484922..5f88ae9e839 100644 --- a/include/llvm/Target/TargetRegInfo.h +++ b/include/llvm/Target/TargetRegInfo.h @@ -39,29 +39,22 @@ class BasicBlock; class MachineRegClassInfo { protected: - const unsigned RegClassID; // integer ID of a reg class const unsigned NumOfAvailRegs; // # of avail for coloring -without SP etc. const unsigned NumOfAllRegs; // # of all registers -including SP,g0 etc. public: - inline unsigned getRegClassID() const { return RegClassID; } inline unsigned getNumOfAvailRegs() const { return NumOfAvailRegs; } inline unsigned getNumOfAllRegs() const { return NumOfAllRegs; } - - // This method should find a color which is not used by neighbors // (i.e., a false position in IsColorUsedArr) and - virtual void colorIGNode(IGNode * Node, bool IsColorUsedArr[] ) const = 0; - virtual bool isRegVolatile(const int Reg) const = 0; - - MachineRegClassInfo(const unsigned ID, const unsigned NVR, - const unsigned NAR): RegClassID(ID), NumOfAvailRegs(NVR), - NumOfAllRegs(NAR) - { } // empty constructor + virtual void colorIGNode(IGNode *Node, bool IsColorUsedArr[]) const = 0; + virtual bool isRegVolatile(int Reg) const = 0; + MachineRegClassInfo(unsigned ID, unsigned NVR, unsigned NAR) + : RegClassID(ID), NumOfAvailRegs(NVR), NumOfAllRegs(NAR) {} }; @@ -74,27 +67,15 @@ public: // //-------------------------------------------------------------------------- - - -typedef std::hash_map AddedInstrMapType; - -// A vector of all machine register classes -// -typedef std::vector MachineRegClassArrayType; - - class MachineRegInfo : public NonCopyableV { -public: - const TargetMachine& target; - protected: - - MachineRegClassArrayType MachineRegClassArr; + // A vector of all machine register classes + // + std::vector MachineRegClassArr; public: + const TargetMachine ⌖ - // empty constructor - // MachineRegInfo(const TargetMachine& tgt) : target(tgt) { } @@ -103,7 +84,7 @@ public: // condition code register. If isCCReg is true below, the ID of the condition // code regiter class will be returned. Otherwise, the normal register // class (eg. int, float) must be returned. - virtual unsigned getRegClassIDOfValue (const Value *const Val, + virtual unsigned getRegClassIDOfValue (const Value *Val, bool isCCReg = false) const =0; @@ -111,37 +92,37 @@ public: return MachineRegClassArr.size(); } - const MachineRegClassInfo *const getMachineRegClass(unsigned i) const { + const MachineRegClassInfo *getMachineRegClass(unsigned i) const { return MachineRegClassArr[i]; } // returns the register that is hardwired to zero if any (-1 if none) // - virtual inline int getZeroRegNum() const = 0; + virtual int getZeroRegNum() const = 0; // The following methods are used to color special live ranges (e.g. // method args and return values etc.) with specific hardware registers // as required. See SparcRegInfo.cpp for the implementation for Sparc. // - virtual void suggestRegs4MethodArgs(const Method *const Meth, - LiveRangeInfo & LRI) const = 0; + virtual void suggestRegs4MethodArgs(const Method *Meth, + LiveRangeInfo &LRI) const = 0; - virtual void suggestRegs4CallArgs(const MachineInstr *const CallI, - LiveRangeInfo& LRI, std::vector RCL) const = 0; + virtual void suggestRegs4CallArgs(const MachineInstr *CallI, + LiveRangeInfo &LRI, std::vector RCL) const = 0; - virtual void suggestReg4RetValue(const MachineInstr *const RetI, - LiveRangeInfo& LRI) const = 0; + virtual void suggestReg4RetValue(const MachineInstr *RetI, + LiveRangeInfo &LRI) const = 0; - virtual void colorMethodArgs(const Method *const Meth, LiveRangeInfo& LRI, - AddedInstrns *const FirstAI) const = 0; + virtual void colorMethodArgs(const Method *Meth, LiveRangeInfo &LRI, + AddedInstrns *FirstAI) const = 0; - virtual void colorCallArgs(const MachineInstr *const CalI, - LiveRangeInfo& LRI, AddedInstrns *const CallAI, + virtual void colorCallArgs(const MachineInstr *CalI, + LiveRangeInfo& LRI, AddedInstrns *CallAI, PhyRegAlloc &PRA, const BasicBlock *BB) const = 0; - virtual void colorRetValue(const MachineInstr *const RetI,LiveRangeInfo& LRI, - AddedInstrns *const RetAI) const = 0; + virtual void colorRetValue(const MachineInstr *RetI, LiveRangeInfo &LRI, + AddedInstrns *RetAI) const = 0; @@ -150,21 +131,18 @@ public: // interface. However, they can be moved to MachineInstrInfo interface if // necessary. // - virtual MachineInstr * - cpReg2RegMI(const unsigned SrcReg, const unsigned DestReg, - const int RegType) const=0; + virtual MachineInstr *cpReg2RegMI(unsigned SrcReg, unsigned DestReg, + int RegType) const = 0; - virtual MachineInstr * - cpReg2MemMI(const unsigned SrcReg, const unsigned DestPtrReg, - const int Offset, const int RegType) const=0; + virtual MachineInstr *cpReg2MemMI(unsigned SrcReg, unsigned DestPtrReg, + int Offset, int RegType) const = 0; - virtual MachineInstr * - cpMem2RegMI(const unsigned SrcPtrReg, const int Offset, - const unsigned DestReg, const int RegType) const=0; + virtual MachineInstr *cpMem2RegMI(unsigned SrcPtrReg, int Offset, + unsigned DestReg, int RegType) const = 0; - virtual MachineInstr *cpValue2Value( Value *Src, Value *Dest) const=0; + virtual MachineInstr *cpValue2Value(Value *Src, Value *Dest) const = 0; - virtual bool isRegVolatile(const int RegClassID, const int Reg) const=0; + virtual bool isRegVolatile(int RegClassID, int Reg) const = 0; @@ -191,21 +169,21 @@ public: // Gives the type of a register based on the type of the LR // - virtual int getRegType(const LiveRange *const LR) const=0; + virtual int getRegType(const LiveRange *LR) const = 0; // Gives the return value contained in a CALL machine instruction // - virtual const Value * getCallInstRetVal(const MachineInstr *CallMI) const=0; + virtual const Value *getCallInstRetVal(const MachineInstr *CallMI) const = 0; // The following methods are used to get the frame/stack pointers // - inline virtual unsigned getFramePointer() const=0; - inline virtual unsigned getStackPointer() const=0; + virtual unsigned getFramePointer() const = 0; + virtual unsigned getStackPointer() const = 0; // A register can be initialized to an invalid number. That number can // be obtained using this method. // - inline virtual int getInvalidRegNum() const=0; + virtual int getInvalidRegNum() const = 0; // Method for inserting caller saving code. The caller must save all the @@ -215,22 +193,12 @@ public: // virtual void insertCallerSavingCode(const MachineInstr *MInst, const BasicBlock *BB, - PhyRegAlloc &PRA ) const = 0; + PhyRegAlloc &PRA) const = 0; // This method gives the the number of bytes of stack spaceallocated // to a register when it is spilled to the stack. // - virtual inline int getSpilledRegSize(const int RegType) const = 0; - - - + virtual int getSpilledRegSize(int RegType) const = 0; }; - - - #endif - - - - diff --git a/include/llvm/Target/TargetSchedInfo.h b/include/llvm/Target/TargetSchedInfo.h index aea0357e20f..12539b686f2 100644 --- a/include/llvm/Target/TargetSchedInfo.h +++ b/include/llvm/Target/TargetSchedInfo.h @@ -1,4 +1,4 @@ -//===-- llvm/Target/SchedInfo.h - Target Instruction Sched Info --*- C++ -*-==// +//===- Target/MachineSchedInfo.h - Target Instruction Sched Info -*- C++ -*-==// // // This file describes the target machine to the instruction scheduler. // @@ -7,12 +7,12 @@ #ifndef LLVM_TARGET_MACHINESCHEDINFO_H #define LLVM_TARGET_MACHINESCHEDINFO_H -#include "llvm/Target/MachineInstrInfo.h" #include +#include "llvm/Target/MachineInstrInfo.h" typedef long long cycles_t; -const cycles_t HUGE_LATENCY = ~((long long) 1 << (sizeof(cycles_t)-2)); -const cycles_t INVALID_LATENCY = -HUGE_LATENCY; +static const cycles_t HUGE_LATENCY = ~((long long) 1 << (sizeof(cycles_t)-2)); +static const cycles_t INVALID_LATENCY = -HUGE_LATENCY; static const unsigned MAX_OPCODE_SIZE = 16; class OpCodePair { @@ -29,11 +29,11 @@ private: }; namespace std { -template <> struct hash { - size_t operator()(const OpCodePair& pair) const { - return hash()(pair.val); - } -}; + template <> struct hash { + size_t operator()(const OpCodePair& pair) const { + return hash()(pair.val); + } + }; } //--------------------------------------------------------------------------- @@ -46,15 +46,14 @@ template <> struct hash { //--------------------------------------------------------------------------- -typedef unsigned int resourceId_t; +typedef unsigned resourceId_t; -class MachineResource { -public: +struct MachineResource { const std::string rname; resourceId_t rid; - /*ctor*/ MachineResource(const std::string& resourceName) - : rname(resourceName), rid(nextId++) {} + MachineResource(const std::string &resourceName) + : rname(resourceName), rid(nextId++) {} private: static resourceId_t nextId; @@ -62,12 +61,11 @@ private: }; -class CPUResource : public MachineResource { -public: - int maxNumUsers; // MAXINT if no restriction +struct CPUResource : public MachineResource { + int maxNumUsers; // MAXINT if no restriction - /*ctor*/ CPUResource(const std::string& rname, int maxUsers) - : MachineResource(rname), maxNumUsers(maxUsers) {} + CPUResource(const std::string& rname, int maxUsers) + : MachineResource(rname), maxNumUsers(maxUsers) {} }; @@ -96,30 +94,30 @@ struct InstrClassRUsage { int totCycles; // Issue restrictions common to instructions in this class - unsigned int maxNumIssue; - bool isSingleIssue; - bool breaksGroup; - cycles_t numBubbles; + unsigned maxNumIssue; + bool isSingleIssue; + bool breaksGroup; + cycles_t numBubbles; // Feasible slots to use for instructions in this class. // The size of vector S[] is `numSlots'. - unsigned int numSlots; - unsigned int feasibleSlots[MAX_NUM_SLOTS]; + unsigned numSlots; + unsigned feasibleSlots[MAX_NUM_SLOTS]; // Resource usages common to instructions in this class. // The size of vector V[] is `numRUEntries'. - unsigned int numRUEntries; + unsigned numRUEntries; struct { resourceId_t resourceId; - unsigned int startCycle; - int numCycles; - } V[MAX_NUM_CYCLES]; + unsigned startCycle; + int numCycles; + } V[MAX_NUM_CYCLES]; }; struct InstrRUsageDelta { MachineOpCode opCode; resourceId_t resourceId; - unsigned int startCycle; + unsigned startCycle; int numCycles; }; @@ -135,10 +133,6 @@ struct InstrIssueDelta { struct InstrRUsage { - /*ctor*/ InstrRUsage () {} - /*ctor*/ InstrRUsage (const InstrRUsage& instrRU); - InstrRUsage& operator= (const InstrRUsage& instrRU); - bool sameAsClass; // Issue restrictions for this instruction @@ -155,122 +149,24 @@ struct InstrRUsage { private: // Conveniences for initializing this structure - InstrRUsage& operator= (const InstrClassRUsage& classRU); - void addIssueDelta (const InstrIssueDelta& delta); - void addUsageDelta (const InstrRUsageDelta& delta); - void setMaxSlots (int maxNumSlots); + void setTo(const InstrClassRUsage& classRU); + + void addIssueDelta(const InstrIssueDelta& delta) { + sameAsClass = false; + isSingleIssue = delta.isSingleIssue; + breaksGroup = delta.breaksGroup; + numBubbles = delta.numBubbles; + } + + void addUsageDelta (const InstrRUsageDelta& delta); + void setMaxSlots (int maxNumSlots) { + feasibleSlots.resize(maxNumSlots); + } friend class MachineSchedInfo; // give access to these functions }; -inline void -InstrRUsage::setMaxSlots(int maxNumSlots) -{ - feasibleSlots.resize(maxNumSlots); -} - -inline InstrRUsage& -InstrRUsage::operator=(const InstrRUsage& instrRU) -{ - sameAsClass = instrRU.sameAsClass; - isSingleIssue = instrRU.isSingleIssue; - breaksGroup = instrRU.breaksGroup; - numBubbles = instrRU.numBubbles; - feasibleSlots = instrRU.feasibleSlots; - numCycles = instrRU.numCycles; - resourcesByCycle = instrRU.resourcesByCycle; - return *this; -} - -inline /*ctor*/ -InstrRUsage::InstrRUsage(const InstrRUsage& instrRU) -{ - *this = instrRU; -} - -inline InstrRUsage& -InstrRUsage::operator=(const InstrClassRUsage& classRU) -{ - sameAsClass = true; - isSingleIssue = classRU.isSingleIssue; - breaksGroup = classRU.breaksGroup; - numBubbles = classRU.numBubbles; - - for (unsigned i=0; i < classRU.numSlots; i++) - { - unsigned slot = classRU.feasibleSlots[i]; - assert(slot < feasibleSlots.size() && "Invalid slot specified!"); - this->feasibleSlots[slot] = true; - } - - this->numCycles = classRU.totCycles; - this->resourcesByCycle.resize(this->numCycles); - - for (unsigned i=0; i < classRU.numRUEntries; i++) - for (unsigned c=classRU.V[i].startCycle, NC = c + classRU.V[i].numCycles; - c < NC; c++) - this->resourcesByCycle[c].push_back(classRU.V[i].resourceId); - - // Sort each resource usage vector by resourceId_t to speed up conflict checking - for (unsigned i=0; i < this->resourcesByCycle.size(); i++) - sort(resourcesByCycle[i].begin(), resourcesByCycle[i].end()); - - return *this; -} - - -inline void -InstrRUsage::addIssueDelta(const InstrIssueDelta& delta) -{ - sameAsClass = false; - isSingleIssue = delta.isSingleIssue; - breaksGroup = delta.breaksGroup; - numBubbles = delta.numBubbles; -} - - -// Add the extra resource usage requirements specified in the delta. -// Note that a negative value of `numCycles' means one entry for that -// resource should be deleted for each cycle. -// -inline void -InstrRUsage::addUsageDelta(const InstrRUsageDelta& delta) -{ - int NC = delta.numCycles; - - this->sameAsClass = false; - - // resize the resources vector if more cycles are specified - unsigned maxCycles = this->numCycles; - maxCycles = std::max(maxCycles, delta.startCycle + abs(NC) - 1); - if (maxCycles > this->numCycles) - { - this->resourcesByCycle.resize(maxCycles); - this->numCycles = maxCycles; - } - - if (NC >= 0) - for (unsigned c=delta.startCycle, last=c+NC-1; c <= last; c++) - this->resourcesByCycle[c].push_back(delta.resourceId); - else - // Remove the resource from all NC cycles. - for (unsigned c=delta.startCycle, last=(c-NC)-1; c <= last; c++) - { - // Look for the resource backwards so we remove the last entry - // for that resource in each cycle. - std::vector& rvec = this->resourcesByCycle[c]; - int r; - for (r = (int) rvec.size(); r >= 0; r--) - if (rvec[r] == delta.resourceId) - {// found last entry for the resource - rvec.erase(rvec.begin() + r); - break; - } - assert(r >= 0 && "Resource to remove was unused in cycle c!"); - } -} - //--------------------------------------------------------------------------- // class MachineSchedInfo // @@ -282,7 +178,7 @@ class MachineSchedInfo : public NonCopyableV { public: const TargetMachine& target; - unsigned int maxNumIssueTotal; + unsigned maxNumIssueTotal; int longestIssueConflict; int branchMispredictPenalty; // 4 for SPARC IIi @@ -312,8 +208,8 @@ public: const InstrClassRUsage* _classRUsages, const InstrRUsageDelta* _usageDeltas, const InstrIssueDelta* _issueDeltas, - unsigned int _numUsageDeltas, - unsigned int _numIssueDeltas); + unsigned _numUsageDeltas, + unsigned _numIssueDeltas); /*dtor*/ virtual ~MachineSchedInfo () {} inline const MachineInstrInfo& getInstrInfo() const { @@ -324,11 +220,11 @@ public: return numSchedClasses; } - inline unsigned int getMaxNumIssueTotal() const { + inline unsigned getMaxNumIssueTotal() const { return maxNumIssueTotal; } - inline unsigned int getMaxIssueForClass(const InstrSchedClass& sc) const { + inline unsigned getMaxIssueForClass(const InstrSchedClass& sc) const { assert(sc >= 0 && sc < numSchedClasses); return classRUsages[sc].maxNumIssue; } @@ -369,7 +265,7 @@ public: return getInstrRUsage(opCode).breaksGroup; } - inline unsigned int numBubblesAfter (MachineOpCode opCode) const { + inline unsigned numBubblesAfter (MachineOpCode opCode) const { return getInstrRUsage(opCode).numBubbles; } @@ -386,8 +282,8 @@ protected: const InstrClassRUsage* classRUsages; // raw array by sclass const InstrRUsageDelta* usageDeltas; // raw array [1:numUsageDeltas] const InstrIssueDelta* issueDeltas; // raw array [1:numIssueDeltas] - unsigned int numUsageDeltas; - unsigned int numIssueDeltas; + unsigned numUsageDeltas; + unsigned numIssueDeltas; std::vector instrRUsages; // indexed by opcode std::hash_map issueGaps; // indexed by opcode pair