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Fix calling convention on ARM if vfp2+ is enabled.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109009 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Rafael Espindola 2010-07-21 11:38:30 +00:00
parent 50fb330b8d
commit bc56501435
2 changed files with 28 additions and 6 deletions
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6
lib/Target/ARM/ARMISelLowering.cpp
View File

@ -831,8 +831,9 @@ static bool f64AssignAAPCS(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
CCState &State, bool CanFail) {
static const unsigned HiRegList[] = { ARM::R0, ARM::R2 };
static const unsigned LoRegList[] = { ARM::R1, ARM::R3 };
static const unsigned ShadowRegList[] = { ARM::R0, ARM::R1 };
unsigned Reg = State.AllocateReg(HiRegList, LoRegList, 2);
unsigned Reg = State.AllocateReg(HiRegList, ShadowRegList, 2);
if (Reg == 0) {
// For the 2nd half of a v2f64, do not just fail.
if (CanFail)
@ -850,6 +851,9 @@ static bool f64AssignAAPCS(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
if (HiRegList[i] == Reg)
break;
unsigned T = State.AllocateReg(LoRegList[i]);
assert(T == LoRegList[i] && "Could not allocate register");
State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, LoRegList[i],
LocVT, LocInfo));

28
test/CodeGen/ARM/arguments.ll
View File

@ -1,11 +1,29 @@
; RUN: llc < %s -mtriple=arm-linux-gnueabi | FileCheck %s -check-prefix=ELF
; RUN: llc < %s -mtriple=arm-apple-darwin | FileCheck %s -check-prefix=DARWIN
; RUN: llc < %s -mtriple=arm-linux-gnueabi -mattr=+vfp2 | FileCheck %s -check-prefix=ELF
; RUN: llc < %s -mtriple=arm-apple-darwin -mattr=+vfp2 | FileCheck %s -check-prefix=DARWIN
define i32 @f(i32 %a, i64 %b) {
define i32 @f1(i32 %a, i64 %b) {
; ELF: f1:
; ELF: mov r0, r2
; DARWIN: f1:
; DARWIN: mov r0, r1
%tmp = call i32 @g(i64 %b)
%tmp = call i32 @g1(i64 %b)
ret i32 %tmp
}
declare i32 @g(i64)
; test that allocating the double to r2/r3 makes r1 unavailable on gnueabi.
define i32 @f2() nounwind optsize {
; ELF: f2:
; ELF: mov r0, #128
; ELF: str r0, [sp]
; DARWIN: f2:
; DARWIN: mov r3, #128
entry:
%0 = tail call i32 (i32, ...)* @g2(i32 5, double 1.600000e+01, i32 128) nounwind optsize ; <i32> [#uses=1]
%not. = icmp ne i32 %0, 128 ; <i1> [#uses=1]
%.0 = zext i1 %not. to i32 ; <i32> [#uses=1]
ret i32 %.0
}
declare i32 @g1(i64)
declare i32 @g2(i32 %i, ...)