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fix rdar://8456412 - llvm-mc crash in encoder on "mov %rdx, %cr8"

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Teaching the code generator about CR8-15, how to rex them up, etc.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114533 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2010-09-22 05:29:50 +00:00
parent f7d4da0c1d
commit bc57c6db4a
4 changed files with 39 additions and 42 deletions
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2
lib/Target/X86/X86InstrInfo.cpp
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@ -2993,6 +2993,8 @@ bool X86InstrInfo::isX86_64ExtendedReg(unsigned RegNo) {
case X86::XMM12: case X86::XMM13: case X86::XMM14: case X86::XMM15:
case X86::YMM8: case X86::YMM9: case X86::YMM10: case X86::YMM11:
case X86::YMM12: case X86::YMM13: case X86::YMM14: case X86::YMM15:
case X86::CR8: case X86::CR9: case X86::CR10: case X86::CR11:
case X86::CR12: case X86::CR13: case X86::CR14: case X86::CR15:
return true;
}
return false;

53
lib/Target/X86/X86RegisterInfo.cpp
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@ -159,46 +159,21 @@ unsigned X86RegisterInfo::getX86RegNum(unsigned RegNo) {
case X86::YMM7: case X86::YMM15: case X86::MM7:
return 7;
case X86::ES:
return 0;
case X86::CS:
return 1;
case X86::SS:
return 2;
case X86::DS:
return 3;
case X86::FS:
return 4;
case X86::GS:
return 5;
case X86::ES: return 0;
case X86::CS: return 1;
case X86::SS: return 2;
case X86::DS: return 3;
case X86::FS: return 4;
case X86::GS: return 5;
case X86::CR0:
return 0;
case X86::CR1:
return 1;
case X86::CR2:
return 2;
case X86::CR3:
return 3;
case X86::CR4:
return 4;
case X86::DR0:
return 0;
case X86::DR1:
return 1;
case X86::DR2:
return 2;
case X86::DR3:
return 3;
case X86::DR4:
return 4;
case X86::DR5:
return 5;
case X86::DR6:
return 6;
case X86::DR7:
return 7;
case X86::CR0: case X86::CR8 : case X86::DR0: return 0;
case X86::CR1: case X86::CR9 : case X86::DR1: return 1;
case X86::CR2: case X86::CR10: case X86::DR2: return 2;
case X86::CR3: case X86::CR11: case X86::DR3: return 3;
case X86::CR4: case X86::CR12: case X86::DR4: return 4;
case X86::CR5: case X86::CR13: case X86::DR5: return 5;
case X86::CR6: case X86::CR14: case X86::DR6: return 6;
case X86::CR7: case X86::CR15: case X86::DR7: return 7;
// Pseudo index registers are equivalent to a "none"
// scaled index (See Intel Manual 2A, table 2-3)

12
lib/Target/X86/X86RegisterInfo.td
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@ -231,7 +231,7 @@ let Namespace = "X86" in {
def DR6 : Register<"dr6">;
def DR7 : Register<"dr7">;
// Condition registers
// Control registers
def CR0 : Register<"cr0">;
def CR1 : Register<"cr1">;
def CR2 : Register<"cr2">;
@ -241,6 +241,13 @@ let Namespace = "X86" in {
def CR6 : Register<"cr6">;
def CR7 : Register<"cr7">;
def CR8 : Register<"cr8">;
def CR9 : Register<"cr9">;
def CR10 : Register<"cr10">;
def CR11 : Register<"cr11">;
def CR12 : Register<"cr12">;
def CR13 : Register<"cr13">;
def CR14 : Register<"cr14">;
def CR15 : Register<"cr15">;
// Pseudo index registers
def EIZ : Register<"eiz">;
@ -456,7 +463,8 @@ def DEBUG_REG : RegisterClass<"X86", [i32], 32,
// Control registers.
def CONTROL_REG : RegisterClass<"X86", [i64], 64,
[CR0, CR1, CR2, CR3, CR4, CR5, CR6, CR7, CR8]> {
[CR0, CR1, CR2, CR3, CR4, CR5, CR6, CR7, CR8,
CR9, CR10, CR11, CR12, CR13, CR14, CR15]> {
}
// GR8_ABCD_L, GR8_ABCD_H, GR16_ABCD, GR32_ABCD, GR64_ABCD - Subclasses of

14
test/MC/AsmParser/X86/x86_instructions.s
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@ -340,4 +340,16 @@ fcmova %st(1), %st(0) // CHECK: fcmovnbe %st(1), %st(0)
// rdar://8456417
.byte 88 + 1 & 15 // CHECK: .byte 9
// rdar://8456412
mov %rdx, %cr0
// CHECK: movq %rdx, %cr0
// CHECK: encoding: [0x0f,0x22,0xc2]
mov %rdx, %cr4
// CHECK: movq %rdx, %cr4
// CHECK: encoding: [0x0f,0x22,0xe2]
mov %rdx, %cr8
// CHECK: movq %rdx, %cr8
// CHECK: encoding: [0x44,0x0f,0x22,0xc2]
mov %rdx, %cr15
// CHECK: movq %rdx, %cr15
// CHECK: encoding: [0x44,0x0f,0x22,0xfa]