mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-02-16 00:33:10 +00:00
Reorganize a bit. No functional change, just moving patterns up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127422 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach
parent
a768c3d45f
commit
bc908cfcc1
@ -3406,238 +3406,7 @@ def SWPB : AIswp<1, (outs GPR:$Rt), (ins GPR:$Rt2, GPR:$Rn), "swpb",
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}
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//===----------------------------------------------------------------------===//
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// TLS Instructions
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//
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// __aeabi_read_tp preserves the registers r1-r3.
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// This is a pseudo inst so that we can get the encoding right,
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// complete with fixup for the aeabi_read_tp function.
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let isCall = 1,
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Defs = [R0, R12, LR, CPSR], Uses = [SP] in {
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def TPsoft : PseudoInst<(outs), (ins), IIC_Br,
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[(set R0, ARMthread_pointer)]>;
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}
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//===----------------------------------------------------------------------===//
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// SJLJ Exception handling intrinsics
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// eh_sjlj_setjmp() is an instruction sequence to store the return
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// address and save #0 in R0 for the non-longjmp case.
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// Since by its nature we may be coming from some other function to get
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// here, and we're using the stack frame for the containing function to
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// save/restore registers, we can't keep anything live in regs across
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// the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
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// when we get here from a longjmp(). We force everthing out of registers
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// except for our own input by listing the relevant registers in Defs. By
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// doing so, we also cause the prologue/epilogue code to actively preserve
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// all of the callee-saved resgisters, which is exactly what we want.
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// A constant value is passed in $val, and we use the location as a scratch.
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//
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// These are pseudo-instructions and are lowered to individual MC-insts, so
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// no encoding information is necessary.
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let Defs =
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[ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, D0,
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D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15,
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D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26, D27, D28, D29, D30,
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D31 ], hasSideEffects = 1, isBarrier = 1 in {
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def Int_eh_sjlj_setjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
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NoItinerary,
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[(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
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Requires<[IsARM, HasVFP2]>;
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}
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let Defs =
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[ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR ],
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hasSideEffects = 1, isBarrier = 1 in {
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def Int_eh_sjlj_setjmp_nofp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
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NoItinerary,
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[(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
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Requires<[IsARM, NoVFP]>;
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}
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// FIXME: Non-Darwin version(s)
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let isBarrier = 1, hasSideEffects = 1, isTerminator = 1,
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Defs = [ R7, LR, SP ] in {
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def Int_eh_sjlj_longjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$scratch),
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NoItinerary,
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[(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
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Requires<[IsARM, IsDarwin]>;
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}
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// eh.sjlj.dispatchsetup pseudo-instruction.
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// This pseudo is used for ARM, Thumb1 and Thumb2. Any differences are
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// handled when the pseudo is expanded (which happens before any passes
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// that need the instruction size).
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let isBarrier = 1, hasSideEffects = 1 in
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def Int_eh_sjlj_dispatchsetup :
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PseudoInst<(outs), (ins GPR:$src), NoItinerary,
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[(ARMeh_sjlj_dispatchsetup GPR:$src)]>,
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Requires<[IsDarwin]>;
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//===----------------------------------------------------------------------===//
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// Non-Instruction Patterns
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//
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// Large immediate handling.
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// 32-bit immediate using two piece so_imms or movw + movt.
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// This is a single pseudo instruction, the benefit is that it can be remat'd
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// as a single unit instead of having to handle reg inputs.
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// FIXME: Remove this when we can do generalized remat.
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let isReMaterializable = 1, isMoveImm = 1 in
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def MOVi32imm : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVix2,
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[(set GPR:$dst, (arm_i32imm:$src))]>,
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Requires<[IsARM]>;
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// Pseudo instruction that combines movw + movt + add pc (if PIC).
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// It also makes it possible to rematerialize the instructions.
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// FIXME: Remove this when we can do generalized remat and when machine licm
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// can properly the instructions.
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let isReMaterializable = 1 in {
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def MOV_ga_pcrel : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
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IIC_iMOVix2addpc,
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[(set GPR:$dst, (ARMWrapperPIC tglobaladdr:$addr))]>,
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Requires<[IsARM, UseMovt]>;
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def MOV_ga_dyn : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
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IIC_iMOVix2,
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[(set GPR:$dst, (ARMWrapperDYN tglobaladdr:$addr))]>,
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Requires<[IsARM, UseMovt]>;
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let AddedComplexity = 10 in
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def MOV_ga_pcrel_ldr : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
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IIC_iMOVix2ld,
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[(set GPR:$dst, (load (ARMWrapperPIC tglobaladdr:$addr)))]>,
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Requires<[IsARM, UseMovt]>;
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} // isReMaterializable
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// ConstantPool, GlobalAddress, and JumpTable
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def : ARMPat<(ARMWrapper tglobaladdr :$dst), (LEApcrel tglobaladdr :$dst)>,
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Requires<[IsARM, DontUseMovt]>;
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def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>;
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def : ARMPat<(ARMWrapper tglobaladdr :$dst), (MOVi32imm tglobaladdr :$dst)>,
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Requires<[IsARM, UseMovt]>;
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def : ARMPat<(ARMWrapperJT tjumptable:$dst, imm:$id),
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(LEApcrelJT tjumptable:$dst, imm:$id)>;
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// TODO: add,sub,and, 3-instr forms?
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// Tail calls
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def : ARMPat<(ARMtcret tcGPR:$dst),
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(TCRETURNri tcGPR:$dst)>, Requires<[IsDarwin]>;
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def : ARMPat<(ARMtcret (i32 tglobaladdr:$dst)),
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(TCRETURNdi texternalsym:$dst)>, Requires<[IsDarwin]>;
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def : ARMPat<(ARMtcret (i32 texternalsym:$dst)),
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(TCRETURNdi texternalsym:$dst)>, Requires<[IsDarwin]>;
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def : ARMPat<(ARMtcret tcGPR:$dst),
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(TCRETURNriND tcGPR:$dst)>, Requires<[IsNotDarwin]>;
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def : ARMPat<(ARMtcret (i32 tglobaladdr:$dst)),
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(TCRETURNdiND texternalsym:$dst)>, Requires<[IsNotDarwin]>;
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def : ARMPat<(ARMtcret (i32 texternalsym:$dst)),
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(TCRETURNdiND texternalsym:$dst)>, Requires<[IsNotDarwin]>;
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// Direct calls
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def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>,
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Requires<[IsARM, IsNotDarwin]>;
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def : ARMPat<(ARMcall texternalsym:$func), (BLr9 texternalsym:$func)>,
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Requires<[IsARM, IsDarwin]>;
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// zextload i1 -> zextload i8
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def : ARMPat<(zextloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
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def : ARMPat<(zextloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
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// extload -> zextload
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def : ARMPat<(extloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
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def : ARMPat<(extloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
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def : ARMPat<(extloadi8 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
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def : ARMPat<(extloadi8 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
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def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>;
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def : ARMPat<(extloadi8 addrmodepc:$addr), (PICLDRB addrmodepc:$addr)>;
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def : ARMPat<(extloadi16 addrmodepc:$addr), (PICLDRH addrmodepc:$addr)>;
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// smul* and smla*
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def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
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(sra (shl GPR:$b, (i32 16)), (i32 16))),
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(SMULBB GPR:$a, GPR:$b)>;
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def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b),
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(SMULBB GPR:$a, GPR:$b)>;
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def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
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(sra GPR:$b, (i32 16))),
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(SMULBT GPR:$a, GPR:$b)>;
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def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, (i32 16))),
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(SMULBT GPR:$a, GPR:$b)>;
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def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)),
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(sra (shl GPR:$b, (i32 16)), (i32 16))),
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(SMULTB GPR:$a, GPR:$b)>;
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def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)), sext_16_node:$b),
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(SMULTB GPR:$a, GPR:$b)>;
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def : ARMV5TEPat<(sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
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(i32 16)),
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(SMULWB GPR:$a, GPR:$b)>;
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def : ARMV5TEPat<(sra (mul GPR:$a, sext_16_node:$b), (i32 16)),
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(SMULWB GPR:$a, GPR:$b)>;
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def : ARMV5TEPat<(add GPR:$acc,
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(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
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(sra (shl GPR:$b, (i32 16)), (i32 16)))),
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(SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
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def : ARMV5TEPat<(add GPR:$acc,
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(mul sext_16_node:$a, sext_16_node:$b)),
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(SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
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def : ARMV5TEPat<(add GPR:$acc,
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(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
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(sra GPR:$b, (i32 16)))),
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(SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
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def : ARMV5TEPat<(add GPR:$acc,
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(mul sext_16_node:$a, (sra GPR:$b, (i32 16)))),
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(SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
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def : ARMV5TEPat<(add GPR:$acc,
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(mul (sra GPR:$a, (i32 16)),
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(sra (shl GPR:$b, (i32 16)), (i32 16)))),
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(SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
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def : ARMV5TEPat<(add GPR:$acc,
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(mul (sra GPR:$a, (i32 16)), sext_16_node:$b)),
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(SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
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def : ARMV5TEPat<(add GPR:$acc,
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(sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
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(i32 16))),
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(SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
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def : ARMV5TEPat<(add GPR:$acc,
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(sra (mul GPR:$a, sext_16_node:$b), (i32 16))),
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(SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
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//===----------------------------------------------------------------------===//
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// Thumb Support
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//
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include "ARMInstrThumb.td"
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//===----------------------------------------------------------------------===//
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// Thumb2 Support
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//
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include "ARMInstrThumb2.td"
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//===----------------------------------------------------------------------===//
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// Floating Point Support
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//
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include "ARMInstrVFP.td"
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//===----------------------------------------------------------------------===//
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// Advanced SIMD (NEON) Support
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//
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include "ARMInstrNEON.td"
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//===----------------------------------------------------------------------===//
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// Coprocessor Instructions. For disassembly only.
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// Coprocessor Instructions.
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//
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def CDP : ABI<0b1110, (outs), (ins p_imm:$cop, i32imm:$opc1,
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@ -3938,3 +3707,235 @@ def MSRi : ABI<0b0011, (outs), (ins msr_mask:$mask, so_imm:$a), NoItinerary,
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let Inst{15-12} = 0b1111;
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let Inst{11-0} = a;
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}
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//===----------------------------------------------------------------------===//
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// TLS Instructions
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//
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// __aeabi_read_tp preserves the registers r1-r3.
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// This is a pseudo inst so that we can get the encoding right,
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// complete with fixup for the aeabi_read_tp function.
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let isCall = 1,
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Defs = [R0, R12, LR, CPSR], Uses = [SP] in {
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def TPsoft : PseudoInst<(outs), (ins), IIC_Br,
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[(set R0, ARMthread_pointer)]>;
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}
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//===----------------------------------------------------------------------===//
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// SJLJ Exception handling intrinsics
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// eh_sjlj_setjmp() is an instruction sequence to store the return
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// address and save #0 in R0 for the non-longjmp case.
|
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// Since by its nature we may be coming from some other function to get
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// here, and we're using the stack frame for the containing function to
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// save/restore registers, we can't keep anything live in regs across
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// the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
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// when we get here from a longjmp(). We force everthing out of registers
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// except for our own input by listing the relevant registers in Defs. By
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// doing so, we also cause the prologue/epilogue code to actively preserve
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// all of the callee-saved resgisters, which is exactly what we want.
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// A constant value is passed in $val, and we use the location as a scratch.
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//
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// These are pseudo-instructions and are lowered to individual MC-insts, so
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// no encoding information is necessary.
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let Defs =
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[ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, D0,
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D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15,
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D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26, D27, D28, D29, D30,
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D31 ], hasSideEffects = 1, isBarrier = 1 in {
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def Int_eh_sjlj_setjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
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NoItinerary,
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[(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
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Requires<[IsARM, HasVFP2]>;
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}
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let Defs =
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[ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR ],
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hasSideEffects = 1, isBarrier = 1 in {
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def Int_eh_sjlj_setjmp_nofp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
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NoItinerary,
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[(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
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Requires<[IsARM, NoVFP]>;
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}
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// FIXME: Non-Darwin version(s)
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let isBarrier = 1, hasSideEffects = 1, isTerminator = 1,
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Defs = [ R7, LR, SP ] in {
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def Int_eh_sjlj_longjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$scratch),
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NoItinerary,
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[(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
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Requires<[IsARM, IsDarwin]>;
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}
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// eh.sjlj.dispatchsetup pseudo-instruction.
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// This pseudo is used for ARM, Thumb1 and Thumb2. Any differences are
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// handled when the pseudo is expanded (which happens before any passes
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// that need the instruction size).
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let isBarrier = 1, hasSideEffects = 1 in
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def Int_eh_sjlj_dispatchsetup :
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PseudoInst<(outs), (ins GPR:$src), NoItinerary,
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[(ARMeh_sjlj_dispatchsetup GPR:$src)]>,
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Requires<[IsDarwin]>;
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//===----------------------------------------------------------------------===//
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// Non-Instruction Patterns
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//
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// Large immediate handling.
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|
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// 32-bit immediate using two piece so_imms or movw + movt.
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// This is a single pseudo instruction, the benefit is that it can be remat'd
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// as a single unit instead of having to handle reg inputs.
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// FIXME: Remove this when we can do generalized remat.
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let isReMaterializable = 1, isMoveImm = 1 in
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def MOVi32imm : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVix2,
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[(set GPR:$dst, (arm_i32imm:$src))]>,
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Requires<[IsARM]>;
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// Pseudo instruction that combines movw + movt + add pc (if PIC).
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// It also makes it possible to rematerialize the instructions.
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// FIXME: Remove this when we can do generalized remat and when machine licm
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// can properly the instructions.
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let isReMaterializable = 1 in {
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def MOV_ga_pcrel : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
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IIC_iMOVix2addpc,
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[(set GPR:$dst, (ARMWrapperPIC tglobaladdr:$addr))]>,
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Requires<[IsARM, UseMovt]>;
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def MOV_ga_dyn : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
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IIC_iMOVix2,
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[(set GPR:$dst, (ARMWrapperDYN tglobaladdr:$addr))]>,
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Requires<[IsARM, UseMovt]>;
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let AddedComplexity = 10 in
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def MOV_ga_pcrel_ldr : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
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IIC_iMOVix2ld,
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[(set GPR:$dst, (load (ARMWrapperPIC tglobaladdr:$addr)))]>,
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Requires<[IsARM, UseMovt]>;
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} // isReMaterializable
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// ConstantPool, GlobalAddress, and JumpTable
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def : ARMPat<(ARMWrapper tglobaladdr :$dst), (LEApcrel tglobaladdr :$dst)>,
|
||||
Requires<[IsARM, DontUseMovt]>;
|
||||
def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>;
|
||||
def : ARMPat<(ARMWrapper tglobaladdr :$dst), (MOVi32imm tglobaladdr :$dst)>,
|
||||
Requires<[IsARM, UseMovt]>;
|
||||
def : ARMPat<(ARMWrapperJT tjumptable:$dst, imm:$id),
|
||||
(LEApcrelJT tjumptable:$dst, imm:$id)>;
|
||||
|
||||
// TODO: add,sub,and, 3-instr forms?
|
||||
|
||||
// Tail calls
|
||||
def : ARMPat<(ARMtcret tcGPR:$dst),
|
||||
(TCRETURNri tcGPR:$dst)>, Requires<[IsDarwin]>;
|
||||
|
||||
def : ARMPat<(ARMtcret (i32 tglobaladdr:$dst)),
|
||||
(TCRETURNdi texternalsym:$dst)>, Requires<[IsDarwin]>;
|
||||
|
||||
def : ARMPat<(ARMtcret (i32 texternalsym:$dst)),
|
||||
(TCRETURNdi texternalsym:$dst)>, Requires<[IsDarwin]>;
|
||||
|
||||
def : ARMPat<(ARMtcret tcGPR:$dst),
|
||||
(TCRETURNriND tcGPR:$dst)>, Requires<[IsNotDarwin]>;
|
||||
|
||||
def : ARMPat<(ARMtcret (i32 tglobaladdr:$dst)),
|
||||
(TCRETURNdiND texternalsym:$dst)>, Requires<[IsNotDarwin]>;
|
||||
|
||||
def : ARMPat<(ARMtcret (i32 texternalsym:$dst)),
|
||||
(TCRETURNdiND texternalsym:$dst)>, Requires<[IsNotDarwin]>;
|
||||
|
||||
// Direct calls
|
||||
def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>,
|
||||
Requires<[IsARM, IsNotDarwin]>;
|
||||
def : ARMPat<(ARMcall texternalsym:$func), (BLr9 texternalsym:$func)>,
|
||||
Requires<[IsARM, IsDarwin]>;
|
||||
|
||||
// zextload i1 -> zextload i8
|
||||
def : ARMPat<(zextloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
|
||||
def : ARMPat<(zextloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
|
||||
|
||||
// extload -> zextload
|
||||
def : ARMPat<(extloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
|
||||
def : ARMPat<(extloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
|
||||
def : ARMPat<(extloadi8 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
|
||||
def : ARMPat<(extloadi8 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
|
||||
|
||||
def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>;
|
||||
|
||||
def : ARMPat<(extloadi8 addrmodepc:$addr), (PICLDRB addrmodepc:$addr)>;
|
||||
def : ARMPat<(extloadi16 addrmodepc:$addr), (PICLDRH addrmodepc:$addr)>;
|
||||
|
||||
// smul* and smla*
|
||||
def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
|
||||
(sra (shl GPR:$b, (i32 16)), (i32 16))),
|
||||
(SMULBB GPR:$a, GPR:$b)>;
|
||||
def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b),
|
||||
(SMULBB GPR:$a, GPR:$b)>;
|
||||
def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
|
||||
(sra GPR:$b, (i32 16))),
|
||||
(SMULBT GPR:$a, GPR:$b)>;
|
||||
def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, (i32 16))),
|
||||
(SMULBT GPR:$a, GPR:$b)>;
|
||||
def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)),
|
||||
(sra (shl GPR:$b, (i32 16)), (i32 16))),
|
||||
(SMULTB GPR:$a, GPR:$b)>;
|
||||
def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)), sext_16_node:$b),
|
||||
(SMULTB GPR:$a, GPR:$b)>;
|
||||
def : ARMV5TEPat<(sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
|
||||
(i32 16)),
|
||||
(SMULWB GPR:$a, GPR:$b)>;
|
||||
def : ARMV5TEPat<(sra (mul GPR:$a, sext_16_node:$b), (i32 16)),
|
||||
(SMULWB GPR:$a, GPR:$b)>;
|
||||
|
||||
def : ARMV5TEPat<(add GPR:$acc,
|
||||
(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
|
||||
(sra (shl GPR:$b, (i32 16)), (i32 16)))),
|
||||
(SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
|
||||
def : ARMV5TEPat<(add GPR:$acc,
|
||||
(mul sext_16_node:$a, sext_16_node:$b)),
|
||||
(SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
|
||||
def : ARMV5TEPat<(add GPR:$acc,
|
||||
(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
|
||||
(sra GPR:$b, (i32 16)))),
|
||||
(SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
|
||||
def : ARMV5TEPat<(add GPR:$acc,
|
||||
(mul sext_16_node:$a, (sra GPR:$b, (i32 16)))),
|
||||
(SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
|
||||
def : ARMV5TEPat<(add GPR:$acc,
|
||||
(mul (sra GPR:$a, (i32 16)),
|
||||
(sra (shl GPR:$b, (i32 16)), (i32 16)))),
|
||||
(SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
|
||||
def : ARMV5TEPat<(add GPR:$acc,
|
||||
(mul (sra GPR:$a, (i32 16)), sext_16_node:$b)),
|
||||
(SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
|
||||
def : ARMV5TEPat<(add GPR:$acc,
|
||||
(sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
|
||||
(i32 16))),
|
||||
(SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
|
||||
def : ARMV5TEPat<(add GPR:$acc,
|
||||
(sra (mul GPR:$a, sext_16_node:$b), (i32 16))),
|
||||
(SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Thumb Support
|
||||
//
|
||||
|
||||
include "ARMInstrThumb.td"
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Thumb2 Support
|
||||
//
|
||||
|
||||
include "ARMInstrThumb2.td"
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Floating Point Support
|
||||
//
|
||||
|
||||
include "ARMInstrVFP.td"
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Advanced SIMD (NEON) Support
|
||||
//
|
||||
|
||||
include "ARMInstrNEON.td"
|
||||
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user