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https://github.com/c64scene-ar/llvm-6502.git
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Properly support v8i8 and v4i16 types. It now converts them to v2i32 for
load and stores. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35002 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -327,9 +327,12 @@ X86TargetLowering::X86TargetLowering(TargetMachine &TM)
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addRegisterClass(MVT::v2i32, X86::VR64RegisterClass);
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// FIXME: add MMX packed arithmetics
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setOperationAction(ISD::LOAD, MVT::v8i8, Legal);
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setOperationAction(ISD::LOAD, MVT::v4i16, Legal);
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setOperationAction(ISD::LOAD, MVT::v8i8, Promote);
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AddPromotedToType (ISD::LOAD, MVT::v8i8, MVT::v2i32);
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setOperationAction(ISD::LOAD, MVT::v4i16, Promote);
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AddPromotedToType (ISD::LOAD, MVT::v4i16, MVT::v2i32);
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setOperationAction(ISD::LOAD, MVT::v2i32, Legal);
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setOperationAction(ISD::BUILD_VECTOR, MVT::v8i8, Expand);
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setOperationAction(ISD::BUILD_VECTOR, MVT::v4i16, Expand);
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setOperationAction(ISD::BUILD_VECTOR, MVT::v2i32, Expand);
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@ -1,4 +1,4 @@
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//====- X86InstrMMX.td - Describe the X86 Instruction Set -------*- C++ -*-===//
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//====- X86InstrMMX.td - Describe the X86 Instruction Set --*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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@ -33,14 +33,17 @@ def IMPLICIT_DEF_VR64 : I<0, Pseudo, (ops VR64:$dst),
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[(set VR64:$dst, (v8i8 (undef)))]>,
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Requires<[HasMMX]>;
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def : Pat<(v8i8 (undef)), (IMPLICIT_DEF_VR64)>, Requires<[HasMMX]>;
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def : Pat<(v4i16 (undef)), (IMPLICIT_DEF_VR64)>, Requires<[HasMMX]>;
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def : Pat<(v2i32 (undef)), (IMPLICIT_DEF_VR64)>, Requires<[HasMMX]>;
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// 64-bit vector undef's.
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def : Pat<(v8i8 (undef)), (IMPLICIT_DEF_VR64)>;
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def : Pat<(v4i16 (undef)), (IMPLICIT_DEF_VR64)>;
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def : Pat<(v2i32 (undef)), (IMPLICIT_DEF_VR64)>;
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//===----------------------------------------------------------------------===//
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// MMX Pattern Fragments
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//===----------------------------------------------------------------------===//
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def loadv8i8 : PatFrag<(ops node:$ptr), (v8i8 (load node:$ptr))>;
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def loadv4i16 : PatFrag<(ops node:$ptr), (v4i16 (load node:$ptr))>;
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def loadv2i32 : PatFrag<(ops node:$ptr), (v2i32 (load node:$ptr))>;
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//===----------------------------------------------------------------------===//
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@ -120,3 +123,11 @@ def : Pat<(store (v8i8 VR64:$src), addr:$dst),
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(MOVQ64mr addr:$dst, VR64:$src)>;
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def : Pat<(store (v4i16 VR64:$src), addr:$dst),
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(MOVQ64mr addr:$dst, VR64:$src)>;
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// Bit convert.
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def : Pat<(v8i8 (bitconvert (v2i32 VR64:$src))), (v8i8 VR64:$src)>;
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def : Pat<(v8i8 (bitconvert (v4i16 VR64:$src))), (v8i8 VR64:$src)>;
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def : Pat<(v4i16 (bitconvert (v2i32 VR64:$src))), (v4i16 VR64:$src)>;
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def : Pat<(v4i16 (bitconvert (v8i8 VR64:$src))), (v4i16 VR64:$src)>;
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def : Pat<(v2i32 (bitconvert (v4i16 VR64:$src))), (v2i32 VR64:$src)>;
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def : Pat<(v2i32 (bitconvert (v8i8 VR64:$src))), (v2i32 VR64:$src)>;
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