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Create a new InstrEmitter class for translating SelectionDAG nodes
into MachineInstrs. This is mostly just moving the code from ScheduleDAGSDNodesEmit.cpp into a new class. This decouples MachineInstr emitting from scheduling. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83699 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -2,6 +2,7 @@ add_llvm_library(LLVMSelectionDAG
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CallingConvLower.cpp
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DAGCombiner.cpp
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FastISel.cpp
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InstrEmitter.cpp
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LegalizeDAG.cpp
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LegalizeFloatTypes.cpp
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LegalizeIntegerTypes.cpp
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@ -13,7 +14,6 @@ add_llvm_library(LLVMSelectionDAG
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ScheduleDAGList.cpp
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ScheduleDAGRRList.cpp
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ScheduleDAGSDNodes.cpp
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ScheduleDAGSDNodesEmit.cpp
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SelectionDAG.cpp
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SelectionDAGBuild.cpp
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SelectionDAGISel.cpp
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@ -1,4 +1,4 @@
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//===---- ScheduleDAGEmit.cpp - Emit routines for the ScheduleDAG class ---===//
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//==--- InstrEmitter.cpp - Emit MachineInstrs for the SelectionDAG class ---==//
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//
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// The LLVM Compiler Infrastructure
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//
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@ -7,13 +7,14 @@
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//
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//===----------------------------------------------------------------------===//
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//
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// This implements the Emit routines for the ScheduleDAG class, which creates
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// MachineInstrs according to the computed schedule.
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// This implements the Emit routines for the SelectionDAG class, which creates
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// MachineInstrs based on the decisions of the SelectionDAG instruction
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// selection.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "pre-RA-sched"
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#include "ScheduleDAGSDNodes.h"
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#define DEBUG_TYPE "instr-emitter"
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#include "InstrEmitter.h"
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#include "llvm/CodeGen/MachineConstantPool.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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@ -29,9 +30,34 @@
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#include "llvm/Support/MathExtras.h"
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using namespace llvm;
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/// CountResults - The results of target nodes have register or immediate
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/// operands first, then an optional chain, and optional flag operands (which do
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/// not go into the resulting MachineInstr).
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unsigned InstrEmitter::CountResults(SDNode *Node) {
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unsigned N = Node->getNumValues();
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while (N && Node->getValueType(N - 1) == MVT::Flag)
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--N;
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if (N && Node->getValueType(N - 1) == MVT::Other)
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--N; // Skip over chain result.
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return N;
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}
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/// CountOperands - The inputs to target nodes have any actual inputs first,
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/// followed by an optional chain operand, then an optional flag operand.
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/// Compute the number of actual operands that will go into the resulting
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/// MachineInstr.
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unsigned InstrEmitter::CountOperands(SDNode *Node) {
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unsigned N = Node->getNumOperands();
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while (N && Node->getOperand(N - 1).getValueType() == MVT::Flag)
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--N;
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if (N && Node->getOperand(N - 1).getValueType() == MVT::Other)
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--N; // Ignore chain if it exists.
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return N;
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}
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/// EmitCopyFromReg - Generate machine code for an CopyFromReg node or an
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/// implicit physical register output.
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void ScheduleDAGSDNodes::
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void InstrEmitter::
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EmitCopyFromReg(SDNode *Node, unsigned ResNo, bool IsClone, bool IsCloned,
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unsigned SrcReg, DenseMap<SDValue, unsigned> &VRBaseMap) {
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unsigned VRBase = 0;
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@ -101,7 +127,7 @@ EmitCopyFromReg(SDNode *Node, unsigned ResNo, bool IsClone, bool IsCloned,
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// Figure out the register class to create for the destreg.
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if (VRBase) {
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DstRC = MRI.getRegClass(VRBase);
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DstRC = MRI->getRegClass(VRBase);
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} else if (UseRC) {
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assert(UseRC->hasType(VT) && "Incompatible phys register def and uses!");
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DstRC = UseRC;
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@ -115,8 +141,8 @@ EmitCopyFromReg(SDNode *Node, unsigned ResNo, bool IsClone, bool IsCloned,
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VRBase = SrcReg;
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} else {
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// Create the reg, emit the copy.
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VRBase = MRI.createVirtualRegister(DstRC);
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bool Emitted = TII->copyRegToReg(*BB, InsertPos, VRBase, SrcReg,
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VRBase = MRI->createVirtualRegister(DstRC);
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bool Emitted = TII->copyRegToReg(*MBB, InsertPos, VRBase, SrcReg,
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DstRC, SrcRC);
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assert(Emitted && "Unable to issue a copy instruction!\n");
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@ -133,7 +159,7 @@ EmitCopyFromReg(SDNode *Node, unsigned ResNo, bool IsClone, bool IsCloned,
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/// getDstOfCopyToRegUse - If the only use of the specified result number of
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/// node is a CopyToReg, return its destination register. Return 0 otherwise.
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unsigned ScheduleDAGSDNodes::getDstOfOnlyCopyToRegUse(SDNode *Node,
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unsigned InstrEmitter::getDstOfOnlyCopyToRegUse(SDNode *Node,
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unsigned ResNo) const {
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if (!Node->hasOneUse())
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return 0;
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@ -149,7 +175,7 @@ unsigned ScheduleDAGSDNodes::getDstOfOnlyCopyToRegUse(SDNode *Node,
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return 0;
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}
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void ScheduleDAGSDNodes::CreateVirtualRegisters(SDNode *Node, MachineInstr *MI,
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void InstrEmitter::CreateVirtualRegisters(SDNode *Node, MachineInstr *MI,
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const TargetInstrDesc &II,
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bool IsClone, bool IsCloned,
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DenseMap<SDValue, unsigned> &VRBaseMap) {
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@ -179,7 +205,7 @@ void ScheduleDAGSDNodes::CreateVirtualRegisters(SDNode *Node, MachineInstr *MI,
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User->getOperand(2).getResNo() == i) {
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unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
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if (TargetRegisterInfo::isVirtualRegister(Reg)) {
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const TargetRegisterClass *RegRC = MRI.getRegClass(Reg);
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const TargetRegisterClass *RegRC = MRI->getRegClass(Reg);
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if (RegRC == RC) {
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VRBase = Reg;
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MI->addOperand(MachineOperand::CreateReg(Reg, true));
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@ -193,7 +219,7 @@ void ScheduleDAGSDNodes::CreateVirtualRegisters(SDNode *Node, MachineInstr *MI,
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// the machine instruction.
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if (VRBase == 0) {
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assert(RC && "Isn't a register operand!");
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VRBase = MRI.createVirtualRegister(RC);
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VRBase = MRI->createVirtualRegister(RC);
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MI->addOperand(MachineOperand::CreateReg(VRBase, true));
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}
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@ -208,7 +234,7 @@ void ScheduleDAGSDNodes::CreateVirtualRegisters(SDNode *Node, MachineInstr *MI,
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/// getVR - Return the virtual register corresponding to the specified result
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/// of the specified node.
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unsigned ScheduleDAGSDNodes::getVR(SDValue Op,
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unsigned InstrEmitter::getVR(SDValue Op,
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DenseMap<SDValue, unsigned> &VRBaseMap) {
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if (Op.isMachineOpcode() &&
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Op.getMachineOpcode() == TargetInstrInfo::IMPLICIT_DEF) {
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@ -218,9 +244,10 @@ unsigned ScheduleDAGSDNodes::getVR(SDValue Op,
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// does not include operand register class info.
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if (!VReg) {
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const TargetRegisterClass *RC = TLI->getRegClassFor(Op.getValueType());
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VReg = MRI.createVirtualRegister(RC);
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VReg = MRI->createVirtualRegister(RC);
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}
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BuildMI(BB, Op.getDebugLoc(), TII->get(TargetInstrInfo::IMPLICIT_DEF),VReg);
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BuildMI(MBB, Op.getDebugLoc(),
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TII->get(TargetInstrInfo::IMPLICIT_DEF), VReg);
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return VReg;
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}
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@ -234,7 +261,7 @@ unsigned ScheduleDAGSDNodes::getVR(SDValue Op,
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/// specified machine instr. Insert register copies if the register is
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/// not in the required register class.
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void
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ScheduleDAGSDNodes::AddRegisterOperand(MachineInstr *MI, SDValue Op,
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InstrEmitter::AddRegisterOperand(MachineInstr *MI, SDValue Op,
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unsigned IIOpNum,
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const TargetInstrDesc *II,
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DenseMap<SDValue, unsigned> &VRBaseMap) {
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@ -252,15 +279,15 @@ ScheduleDAGSDNodes::AddRegisterOperand(MachineInstr *MI, SDValue Op,
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// If the instruction requires a register in a different class, create
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// a new virtual register and copy the value into it.
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if (II) {
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const TargetRegisterClass *SrcRC = MRI.getRegClass(VReg);
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const TargetRegisterClass *SrcRC = MRI->getRegClass(VReg);
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const TargetRegisterClass *DstRC = 0;
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if (IIOpNum < II->getNumOperands())
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DstRC = II->OpInfo[IIOpNum].getRegClass(TRI);
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assert((DstRC || (TID.isVariadic() && IIOpNum >= TID.getNumOperands())) &&
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"Don't have operand info for this instruction!");
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if (DstRC && SrcRC != DstRC && !SrcRC->hasSuperClass(DstRC)) {
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unsigned NewVReg = MRI.createVirtualRegister(DstRC);
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bool Emitted = TII->copyRegToReg(*BB, InsertPos, NewVReg, VReg,
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unsigned NewVReg = MRI->createVirtualRegister(DstRC);
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bool Emitted = TII->copyRegToReg(*MBB, InsertPos, NewVReg, VReg,
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DstRC, SrcRC);
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assert(Emitted && "Unable to issue a copy instruction!\n");
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(void) Emitted;
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@ -275,7 +302,7 @@ ScheduleDAGSDNodes::AddRegisterOperand(MachineInstr *MI, SDValue Op,
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/// specifies the instruction information for the node, and IIOpNum is the
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/// operand number (in the II) that we are adding. IIOpNum and II are used for
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/// assertions only.
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void ScheduleDAGSDNodes::AddOperand(MachineInstr *MI, SDValue Op,
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void InstrEmitter::AddOperand(MachineInstr *MI, SDValue Op,
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unsigned IIOpNum,
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const TargetInstrDesc *II,
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DenseMap<SDValue, unsigned> &VRBaseMap) {
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@ -304,18 +331,19 @@ void ScheduleDAGSDNodes::AddOperand(MachineInstr *MI, SDValue Op,
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const Type *Type = CP->getType();
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// MachineConstantPool wants an explicit alignment.
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if (Align == 0) {
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Align = TM.getTargetData()->getPrefTypeAlignment(Type);
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Align = TM->getTargetData()->getPrefTypeAlignment(Type);
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if (Align == 0) {
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// Alignment of vector types. FIXME!
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Align = TM.getTargetData()->getTypeAllocSize(Type);
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Align = TM->getTargetData()->getTypeAllocSize(Type);
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}
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}
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unsigned Idx;
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MachineConstantPool *MCP = MF->getConstantPool();
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if (CP->isMachineConstantPoolEntry())
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Idx = ConstPool->getConstantPoolIndex(CP->getMachineCPVal(), Align);
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Idx = MCP->getConstantPoolIndex(CP->getMachineCPVal(), Align);
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else
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Idx = ConstPool->getConstantPoolIndex(CP->getConstVal(), Align);
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Idx = MCP->getConstantPoolIndex(CP->getConstVal(), Align);
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MI->addOperand(MachineOperand::CreateCPI(Idx, Offset,
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CP->getTargetFlags()));
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} else if (ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(Op)) {
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@ -346,7 +374,7 @@ getSuperRegisterRegClass(const TargetRegisterClass *TRC,
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/// EmitSubregNode - Generate machine code for subreg nodes.
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///
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void ScheduleDAGSDNodes::EmitSubregNode(SDNode *Node,
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void InstrEmitter::EmitSubregNode(SDNode *Node,
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DenseMap<SDValue, unsigned> &VRBaseMap){
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unsigned VRBase = 0;
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unsigned Opc = Node->getMachineOpcode();
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@ -370,12 +398,12 @@ void ScheduleDAGSDNodes::EmitSubregNode(SDNode *Node,
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unsigned SubIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
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// Create the extract_subreg machine instruction.
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MachineInstr *MI = BuildMI(MF, Node->getDebugLoc(),
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MachineInstr *MI = BuildMI(*MF, Node->getDebugLoc(),
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TII->get(TargetInstrInfo::EXTRACT_SUBREG));
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// Figure out the register class to create for the destreg.
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unsigned VReg = getVR(Node->getOperand(0), VRBaseMap);
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const TargetRegisterClass *TRC = MRI.getRegClass(VReg);
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const TargetRegisterClass *TRC = MRI->getRegClass(VReg);
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const TargetRegisterClass *SRC = TRC->getSubRegisterRegClass(SubIdx);
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assert(SRC && "Invalid subregister index in EXTRACT_SUBREG");
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@ -383,17 +411,17 @@ void ScheduleDAGSDNodes::EmitSubregNode(SDNode *Node,
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// Note that if we're going to directly use an existing register,
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// it must be precisely the required class, and not a subclass
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// thereof.
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if (VRBase == 0 || SRC != MRI.getRegClass(VRBase)) {
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if (VRBase == 0 || SRC != MRI->getRegClass(VRBase)) {
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// Create the reg
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assert(SRC && "Couldn't find source register class");
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VRBase = MRI.createVirtualRegister(SRC);
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VRBase = MRI->createVirtualRegister(SRC);
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}
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// Add def, source, and subreg index
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MI->addOperand(MachineOperand::CreateReg(VRBase, true));
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AddOperand(MI, Node->getOperand(0), 0, 0, VRBaseMap);
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MI->addOperand(MachineOperand::CreateImm(SubIdx));
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BB->insert(InsertPos, MI);
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MBB->insert(InsertPos, MI);
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} else if (Opc == TargetInstrInfo::INSERT_SUBREG ||
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Opc == TargetInstrInfo::SUBREG_TO_REG) {
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SDValue N0 = Node->getOperand(0);
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@ -401,7 +429,7 @@ void ScheduleDAGSDNodes::EmitSubregNode(SDNode *Node,
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SDValue N2 = Node->getOperand(2);
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unsigned SubReg = getVR(N1, VRBaseMap);
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unsigned SubIdx = cast<ConstantSDNode>(N2)->getZExtValue();
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const TargetRegisterClass *TRC = MRI.getRegClass(SubReg);
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const TargetRegisterClass *TRC = MRI->getRegClass(SubReg);
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const TargetRegisterClass *SRC =
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getSuperRegisterRegClass(TRC, SubIdx,
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Node->getValueType(0));
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@ -410,14 +438,14 @@ void ScheduleDAGSDNodes::EmitSubregNode(SDNode *Node,
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// Note that if we're going to directly use an existing register,
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// it must be precisely the required class, and not a subclass
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// thereof.
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if (VRBase == 0 || SRC != MRI.getRegClass(VRBase)) {
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if (VRBase == 0 || SRC != MRI->getRegClass(VRBase)) {
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// Create the reg
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assert(SRC && "Couldn't find source register class");
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VRBase = MRI.createVirtualRegister(SRC);
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VRBase = MRI->createVirtualRegister(SRC);
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}
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// Create the insert_subreg or subreg_to_reg machine instruction.
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MachineInstr *MI = BuildMI(MF, Node->getDebugLoc(), TII->get(Opc));
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MachineInstr *MI = BuildMI(*MF, Node->getDebugLoc(), TII->get(Opc));
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MI->addOperand(MachineOperand::CreateReg(VRBase, true));
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// If creating a subreg_to_reg, then the first input operand
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@ -430,7 +458,7 @@ void ScheduleDAGSDNodes::EmitSubregNode(SDNode *Node,
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// Add the subregster being inserted
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AddOperand(MI, N1, 0, 0, VRBaseMap);
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MI->addOperand(MachineOperand::CreateImm(SubIdx));
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BB->insert(InsertPos, MI);
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MBB->insert(InsertPos, MI);
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} else
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llvm_unreachable("Node is not insert_subreg, extract_subreg, or subreg_to_reg");
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@ -445,17 +473,17 @@ void ScheduleDAGSDNodes::EmitSubregNode(SDNode *Node,
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/// register is constrained to be in a particular register class.
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///
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void
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ScheduleDAGSDNodes::EmitCopyToRegClassNode(SDNode *Node,
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InstrEmitter::EmitCopyToRegClassNode(SDNode *Node,
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DenseMap<SDValue, unsigned> &VRBaseMap) {
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unsigned VReg = getVR(Node->getOperand(0), VRBaseMap);
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const TargetRegisterClass *SrcRC = MRI.getRegClass(VReg);
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const TargetRegisterClass *SrcRC = MRI->getRegClass(VReg);
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unsigned DstRCIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
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const TargetRegisterClass *DstRC = TRI->getRegClass(DstRCIdx);
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// Create the new VReg in the destination class and emit a copy.
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unsigned NewVReg = MRI.createVirtualRegister(DstRC);
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bool Emitted = TII->copyRegToReg(*BB, InsertPos, NewVReg, VReg,
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unsigned NewVReg = MRI->createVirtualRegister(DstRC);
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bool Emitted = TII->copyRegToReg(*MBB, InsertPos, NewVReg, VReg,
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DstRC, SrcRC);
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assert(Emitted &&
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"Unable to issue a copy instruction for a COPY_TO_REGCLASS node!\n");
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@ -469,7 +497,7 @@ ScheduleDAGSDNodes::EmitCopyToRegClassNode(SDNode *Node,
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/// EmitNode - Generate machine code for an node and needed dependencies.
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///
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void ScheduleDAGSDNodes::EmitNode(SDNode *Node, bool IsClone, bool IsCloned,
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void InstrEmitter::EmitNode(SDNode *Node, bool IsClone, bool IsCloned,
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DenseMap<SDValue, unsigned> &VRBaseMap,
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DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) {
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// If machine instruction
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@ -507,7 +535,7 @@ void ScheduleDAGSDNodes::EmitNode(SDNode *Node, bool IsClone, bool IsCloned,
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#endif
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// Create the new machine instruction.
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MachineInstr *MI = BuildMI(MF, Node->getDebugLoc(), II);
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MachineInstr *MI = BuildMI(*MF, Node->getDebugLoc(), II);
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// Add result register values for things that are defined by this
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// instruction.
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@ -531,10 +559,10 @@ void ScheduleDAGSDNodes::EmitNode(SDNode *Node, bool IsClone, bool IsCloned,
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if (II.usesCustomDAGSchedInsertionHook()) {
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// Insert this instruction into the basic block using a target
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// specific inserter which may returns a new basic block.
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BB = TLI->EmitInstrWithCustomInserter(MI, BB, EM);
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InsertPos = BB->end();
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MBB = TLI->EmitInstrWithCustomInserter(MI, MBB, EM);
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InsertPos = MBB->end();
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} else {
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BB->insert(InsertPos, MI);
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MBB->insert(InsertPos, MI);
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}
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// Additional results must be an physical register def.
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@ -551,7 +579,7 @@ void ScheduleDAGSDNodes::EmitNode(SDNode *Node, bool IsClone, bool IsCloned,
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switch (Node->getOpcode()) {
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default:
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#ifndef NDEBUG
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Node->dump(DAG);
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Node->dump();
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#endif
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llvm_unreachable("This target-independent node should have been selected!");
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break;
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@ -576,17 +604,17 @@ void ScheduleDAGSDNodes::EmitNode(SDNode *Node, bool IsClone, bool IsCloned,
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const TargetRegisterClass *SrcTRC = 0, *DstTRC = 0;
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// Get the register classes of the src/dst.
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if (TargetRegisterInfo::isVirtualRegister(SrcReg))
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SrcTRC = MRI.getRegClass(SrcReg);
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SrcTRC = MRI->getRegClass(SrcReg);
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else
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SrcTRC = TRI->getPhysicalRegisterRegClass(SrcReg,SrcVal.getValueType());
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if (TargetRegisterInfo::isVirtualRegister(DestReg))
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DstTRC = MRI.getRegClass(DestReg);
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DstTRC = MRI->getRegClass(DestReg);
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else
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DstTRC = TRI->getPhysicalRegisterRegClass(DestReg,
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Node->getOperand(1).getValueType());
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|
||||
bool Emitted = TII->copyRegToReg(*BB, InsertPos, DestReg, SrcReg,
|
||||
bool Emitted = TII->copyRegToReg(*MBB, InsertPos, DestReg, SrcReg,
|
||||
DstTRC, SrcTRC);
|
||||
assert(Emitted && "Unable to issue a copy instruction!\n");
|
||||
(void) Emitted;
|
||||
@ -603,7 +631,7 @@ void ScheduleDAGSDNodes::EmitNode(SDNode *Node, bool IsClone, bool IsCloned,
|
||||
--NumOps; // Ignore the flag operand.
|
||||
|
||||
// Create the inline asm machine instruction.
|
||||
MachineInstr *MI = BuildMI(MF, Node->getDebugLoc(),
|
||||
MachineInstr *MI = BuildMI(*MF, Node->getDebugLoc(),
|
||||
TII->get(TargetInstrInfo::INLINEASM));
|
||||
|
||||
// Add the asm string as an external symbol operand.
|
||||
@ -645,44 +673,21 @@ void ScheduleDAGSDNodes::EmitNode(SDNode *Node, bool IsClone, bool IsCloned,
|
||||
break;
|
||||
}
|
||||
}
|
||||
BB->insert(InsertPos, MI);
|
||||
MBB->insert(InsertPos, MI);
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/// EmitSchedule - Emit the machine code in scheduled order.
|
||||
MachineBasicBlock *ScheduleDAGSDNodes::
|
||||
EmitSchedule(DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) {
|
||||
DenseMap<SDValue, unsigned> VRBaseMap;
|
||||
DenseMap<SUnit*, unsigned> CopyVRBaseMap;
|
||||
for (unsigned i = 0, e = Sequence.size(); i != e; i++) {
|
||||
SUnit *SU = Sequence[i];
|
||||
if (!SU) {
|
||||
// Null SUnit* is a noop.
|
||||
EmitNoop();
|
||||
continue;
|
||||
}
|
||||
|
||||
// For pre-regalloc scheduling, create instructions corresponding to the
|
||||
// SDNode and any flagged SDNodes and append them to the block.
|
||||
if (!SU->getNode()) {
|
||||
// Emit a copy.
|
||||
EmitPhysRegCopy(SU, CopyVRBaseMap);
|
||||
continue;
|
||||
}
|
||||
|
||||
SmallVector<SDNode *, 4> FlaggedNodes;
|
||||
for (SDNode *N = SU->getNode()->getFlaggedNode(); N;
|
||||
N = N->getFlaggedNode())
|
||||
FlaggedNodes.push_back(N);
|
||||
while (!FlaggedNodes.empty()) {
|
||||
EmitNode(FlaggedNodes.back(), SU->OrigNode != SU, SU->isCloned,
|
||||
VRBaseMap, EM);
|
||||
FlaggedNodes.pop_back();
|
||||
}
|
||||
EmitNode(SU->getNode(), SU->OrigNode != SU, SU->isCloned, VRBaseMap, EM);
|
||||
}
|
||||
|
||||
return BB;
|
||||
/// InstrEmitter - Construct an InstrEmitter and set it to start inserting
|
||||
/// at the given position in the given block.
|
||||
InstrEmitter::InstrEmitter(MachineBasicBlock *mbb,
|
||||
MachineBasicBlock::iterator insertpos)
|
||||
: MF(mbb->getParent()),
|
||||
MRI(&MF->getRegInfo()),
|
||||
TM(&MF->getTarget()),
|
||||
TII(TM->getInstrInfo()),
|
||||
TRI(TM->getRegisterInfo()),
|
||||
TLI(TM->getTargetLowering()),
|
||||
MBB(mbb), InsertPos(insertpos) {
|
||||
}
|
119
lib/CodeGen/SelectionDAG/InstrEmitter.h
Normal file
119
lib/CodeGen/SelectionDAG/InstrEmitter.h
Normal file
@ -0,0 +1,119 @@
|
||||
//===---- InstrEmitter.h - Emit MachineInstrs for the SelectionDAG class ---==//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
// This file is distributed under the University of Illinois Open Source
|
||||
// License. See LICENSE.TXT for details.
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
//
|
||||
// This declares the Emit routines for the SelectionDAG class, which creates
|
||||
// MachineInstrs based on the decisions of the SelectionDAG instruction
|
||||
// selection.
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
#ifndef INSTREMITTER_H
|
||||
#define INSTREMITTER_H
|
||||
|
||||
#include "llvm/CodeGen/SelectionDAG.h"
|
||||
#include "llvm/CodeGen/MachineBasicBlock.h"
|
||||
#include "llvm/ADT/DenseMap.h"
|
||||
|
||||
namespace llvm {
|
||||
|
||||
class TargetInstrDesc;
|
||||
|
||||
class InstrEmitter {
|
||||
MachineFunction *MF;
|
||||
MachineRegisterInfo *MRI;
|
||||
const TargetMachine *TM;
|
||||
const TargetInstrInfo *TII;
|
||||
const TargetRegisterInfo *TRI;
|
||||
const TargetLowering *TLI;
|
||||
|
||||
MachineBasicBlock *MBB;
|
||||
MachineBasicBlock::iterator InsertPos;
|
||||
|
||||
/// EmitCopyFromReg - Generate machine code for an CopyFromReg node or an
|
||||
/// implicit physical register output.
|
||||
void EmitCopyFromReg(SDNode *Node, unsigned ResNo,
|
||||
bool IsClone, bool IsCloned,
|
||||
unsigned SrcReg,
|
||||
DenseMap<SDValue, unsigned> &VRBaseMap);
|
||||
|
||||
/// getDstOfCopyToRegUse - If the only use of the specified result number of
|
||||
/// node is a CopyToReg, return its destination register. Return 0 otherwise.
|
||||
unsigned getDstOfOnlyCopyToRegUse(SDNode *Node,
|
||||
unsigned ResNo) const;
|
||||
|
||||
void CreateVirtualRegisters(SDNode *Node, MachineInstr *MI,
|
||||
const TargetInstrDesc &II,
|
||||
bool IsClone, bool IsCloned,
|
||||
DenseMap<SDValue, unsigned> &VRBaseMap);
|
||||
|
||||
/// getVR - Return the virtual register corresponding to the specified result
|
||||
/// of the specified node.
|
||||
unsigned getVR(SDValue Op,
|
||||
DenseMap<SDValue, unsigned> &VRBaseMap);
|
||||
|
||||
/// AddRegisterOperand - Add the specified register as an operand to the
|
||||
/// specified machine instr. Insert register copies if the register is
|
||||
/// not in the required register class.
|
||||
void AddRegisterOperand(MachineInstr *MI, SDValue Op,
|
||||
unsigned IIOpNum,
|
||||
const TargetInstrDesc *II,
|
||||
DenseMap<SDValue, unsigned> &VRBaseMap);
|
||||
|
||||
/// AddOperand - Add the specified operand to the specified machine instr. II
|
||||
/// specifies the instruction information for the node, and IIOpNum is the
|
||||
/// operand number (in the II) that we are adding. IIOpNum and II are used for
|
||||
/// assertions only.
|
||||
void AddOperand(MachineInstr *MI, SDValue Op,
|
||||
unsigned IIOpNum,
|
||||
const TargetInstrDesc *II,
|
||||
DenseMap<SDValue, unsigned> &VRBaseMap);
|
||||
|
||||
/// EmitSubregNode - Generate machine code for subreg nodes.
|
||||
///
|
||||
void EmitSubregNode(SDNode *Node, DenseMap<SDValue, unsigned> &VRBaseMap);
|
||||
|
||||
/// EmitCopyToRegClassNode - Generate machine code for COPY_TO_REGCLASS nodes.
|
||||
/// COPY_TO_REGCLASS is just a normal copy, except that the destination
|
||||
/// register is constrained to be in a particular register class.
|
||||
///
|
||||
void EmitCopyToRegClassNode(SDNode *Node,
|
||||
DenseMap<SDValue, unsigned> &VRBaseMap);
|
||||
|
||||
public:
|
||||
/// CountResults - The results of target nodes have register or immediate
|
||||
/// operands first, then an optional chain, and optional flag operands
|
||||
/// (which do not go into the machine instrs.)
|
||||
static unsigned CountResults(SDNode *Node);
|
||||
|
||||
/// CountOperands - The inputs to target nodes have any actual inputs first,
|
||||
/// followed by an optional chain operand, then flag operands. Compute
|
||||
/// the number of actual operands that will go into the resulting
|
||||
/// MachineInstr.
|
||||
static unsigned CountOperands(SDNode *Node);
|
||||
|
||||
/// EmitNode - Generate machine code for an node and needed dependencies.
|
||||
///
|
||||
void EmitNode(SDNode *Node, bool IsClone, bool IsCloned,
|
||||
DenseMap<SDValue, unsigned> &VRBaseMap,
|
||||
DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM);
|
||||
|
||||
/// getBlock - Return the current basic block.
|
||||
MachineBasicBlock *getBlock() { return MBB; }
|
||||
|
||||
/// getInsertPos - Return the current insertion position.
|
||||
MachineBasicBlock::iterator getInsertPos() { return InsertPos; }
|
||||
|
||||
/// InstrEmitter - Construct an InstrEmitter and set it to start inserting
|
||||
/// at the given position in the given block.
|
||||
InstrEmitter(MachineBasicBlock *mbb, MachineBasicBlock::iterator insertpos);
|
||||
};
|
||||
|
||||
}
|
||||
|
||||
#endif
|
@ -14,6 +14,7 @@
|
||||
|
||||
#define DEBUG_TYPE "pre-RA-sched"
|
||||
#include "ScheduleDAGSDNodes.h"
|
||||
#include "InstrEmitter.h"
|
||||
#include "llvm/CodeGen/SelectionDAG.h"
|
||||
#include "llvm/Target/TargetMachine.h"
|
||||
#include "llvm/Target/TargetInstrInfo.h"
|
||||
@ -181,7 +182,7 @@ void ScheduleDAGSDNodes::AddSchedEdges() {
|
||||
if (N->isMachineOpcode() &&
|
||||
TII->get(N->getMachineOpcode()).getImplicitDefs()) {
|
||||
SU->hasPhysRegClobbers = true;
|
||||
unsigned NumUsed = CountResults(N);
|
||||
unsigned NumUsed = InstrEmitter::CountResults(N);
|
||||
while (NumUsed != 0 && !N->hasAnyUseOfValue(NumUsed - 1))
|
||||
--NumUsed; // Skip over unused values at the end.
|
||||
if (NumUsed > TII->get(N->getMachineOpcode()).getNumDefs())
|
||||
@ -250,31 +251,6 @@ void ScheduleDAGSDNodes::ComputeLatency(SUnit *SU) {
|
||||
}
|
||||
}
|
||||
|
||||
/// CountResults - The results of target nodes have register or immediate
|
||||
/// operands first, then an optional chain, and optional flag operands (which do
|
||||
/// not go into the resulting MachineInstr).
|
||||
unsigned ScheduleDAGSDNodes::CountResults(SDNode *Node) {
|
||||
unsigned N = Node->getNumValues();
|
||||
while (N && Node->getValueType(N - 1) == MVT::Flag)
|
||||
--N;
|
||||
if (N && Node->getValueType(N - 1) == MVT::Other)
|
||||
--N; // Skip over chain result.
|
||||
return N;
|
||||
}
|
||||
|
||||
/// CountOperands - The inputs to target nodes have any actual inputs first,
|
||||
/// followed by an optional chain operand, then an optional flag operand.
|
||||
/// Compute the number of actual operands that will go into the resulting
|
||||
/// MachineInstr.
|
||||
unsigned ScheduleDAGSDNodes::CountOperands(SDNode *Node) {
|
||||
unsigned N = Node->getNumOperands();
|
||||
while (N && Node->getOperand(N - 1).getValueType() == MVT::Flag)
|
||||
--N;
|
||||
if (N && Node->getOperand(N - 1).getValueType() == MVT::Other)
|
||||
--N; // Ignore chain if it exists.
|
||||
return N;
|
||||
}
|
||||
|
||||
void ScheduleDAGSDNodes::dumpNode(const SUnit *SU) const {
|
||||
if (!SU->getNode()) {
|
||||
errs() << "PHYS REG COPY\n";
|
||||
@ -293,3 +269,43 @@ void ScheduleDAGSDNodes::dumpNode(const SUnit *SU) const {
|
||||
FlaggedNodes.pop_back();
|
||||
}
|
||||
}
|
||||
|
||||
/// EmitSchedule - Emit the machine code in scheduled order.
|
||||
MachineBasicBlock *ScheduleDAGSDNodes::
|
||||
EmitSchedule(DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) {
|
||||
InstrEmitter Emitter(BB, InsertPos);
|
||||
DenseMap<SDValue, unsigned> VRBaseMap;
|
||||
DenseMap<SUnit*, unsigned> CopyVRBaseMap;
|
||||
for (unsigned i = 0, e = Sequence.size(); i != e; i++) {
|
||||
SUnit *SU = Sequence[i];
|
||||
if (!SU) {
|
||||
// Null SUnit* is a noop.
|
||||
EmitNoop();
|
||||
continue;
|
||||
}
|
||||
|
||||
// For pre-regalloc scheduling, create instructions corresponding to the
|
||||
// SDNode and any flagged SDNodes and append them to the block.
|
||||
if (!SU->getNode()) {
|
||||
// Emit a copy.
|
||||
EmitPhysRegCopy(SU, CopyVRBaseMap);
|
||||
continue;
|
||||
}
|
||||
|
||||
SmallVector<SDNode *, 4> FlaggedNodes;
|
||||
for (SDNode *N = SU->getNode()->getFlaggedNode(); N;
|
||||
N = N->getFlaggedNode())
|
||||
FlaggedNodes.push_back(N);
|
||||
while (!FlaggedNodes.empty()) {
|
||||
Emitter.EmitNode(FlaggedNodes.back(), SU->OrigNode != SU, SU->isCloned,
|
||||
VRBaseMap, EM);
|
||||
FlaggedNodes.pop_back();
|
||||
}
|
||||
Emitter.EmitNode(SU->getNode(), SU->OrigNode != SU, SU->isCloned,
|
||||
VRBaseMap, EM);
|
||||
}
|
||||
|
||||
BB = Emitter.getBlock();
|
||||
InsertPos = Emitter.getInsertPos();
|
||||
return BB;
|
||||
}
|
||||
|
@ -92,25 +92,6 @@ namespace llvm {
|
||||
///
|
||||
virtual void ComputeLatency(SUnit *SU);
|
||||
|
||||
/// CountResults - The results of target nodes have register or immediate
|
||||
/// operands first, then an optional chain, and optional flag operands
|
||||
/// (which do not go into the machine instrs.)
|
||||
static unsigned CountResults(SDNode *Node);
|
||||
|
||||
/// CountOperands - The inputs to target nodes have any actual inputs first,
|
||||
/// followed by an optional chain operand, then flag operands. Compute
|
||||
/// the number of actual operands that will go into the resulting
|
||||
/// MachineInstr.
|
||||
static unsigned CountOperands(SDNode *Node);
|
||||
|
||||
/// EmitNode - Generate machine code for an node and needed dependencies.
|
||||
/// VRBaseMap contains, for each already emitted node, the first virtual
|
||||
/// register number for the results of the node.
|
||||
///
|
||||
void EmitNode(SDNode *Node, bool IsClone, bool HasClone,
|
||||
DenseMap<SDValue, unsigned> &VRBaseMap,
|
||||
DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM);
|
||||
|
||||
virtual MachineBasicBlock *
|
||||
EmitSchedule(DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM);
|
||||
|
||||
@ -126,47 +107,6 @@ namespace llvm {
|
||||
virtual void getCustomGraphFeatures(GraphWriter<ScheduleDAG*> &GW) const;
|
||||
|
||||
private:
|
||||
/// EmitSubregNode - Generate machine code for subreg nodes.
|
||||
///
|
||||
void EmitSubregNode(SDNode *Node,
|
||||
DenseMap<SDValue, unsigned> &VRBaseMap);
|
||||
|
||||
/// EmitCopyToRegClassNode - Generate machine code for COPY_TO_REGCLASS
|
||||
/// nodes.
|
||||
///
|
||||
void EmitCopyToRegClassNode(SDNode *Node,
|
||||
DenseMap<SDValue, unsigned> &VRBaseMap);
|
||||
|
||||
/// getVR - Return the virtual register corresponding to the specified result
|
||||
/// of the specified node.
|
||||
unsigned getVR(SDValue Op, DenseMap<SDValue, unsigned> &VRBaseMap);
|
||||
|
||||
/// getDstOfCopyToRegUse - If the only use of the specified result number of
|
||||
/// node is a CopyToReg, return its destination register. Return 0 otherwise.
|
||||
unsigned getDstOfOnlyCopyToRegUse(SDNode *Node, unsigned ResNo) const;
|
||||
|
||||
void AddOperand(MachineInstr *MI, SDValue Op, unsigned IIOpNum,
|
||||
const TargetInstrDesc *II,
|
||||
DenseMap<SDValue, unsigned> &VRBaseMap);
|
||||
|
||||
/// AddRegisterOperand - Add the specified register as an operand to the
|
||||
/// specified machine instr. Insert register copies if the register is
|
||||
/// not in the required register class.
|
||||
void AddRegisterOperand(MachineInstr *MI, SDValue Op,
|
||||
unsigned IIOpNum, const TargetInstrDesc *II,
|
||||
DenseMap<SDValue, unsigned> &VRBaseMap);
|
||||
|
||||
/// EmitCopyFromReg - Generate machine code for an CopyFromReg node or an
|
||||
/// implicit physical register output.
|
||||
void EmitCopyFromReg(SDNode *Node, unsigned ResNo, bool IsClone,
|
||||
bool IsCloned, unsigned SrcReg,
|
||||
DenseMap<SDValue, unsigned> &VRBaseMap);
|
||||
|
||||
void CreateVirtualRegisters(SDNode *Node, MachineInstr *MI,
|
||||
const TargetInstrDesc &II, bool IsClone,
|
||||
bool IsCloned,
|
||||
DenseMap<SDValue, unsigned> &VRBaseMap);
|
||||
|
||||
/// BuildSchedUnits, AddSchedEdges - Helper functions for BuildSchedGraph.
|
||||
void BuildSchedUnits();
|
||||
void AddSchedEdges();
|
||||
|
Loading…
Reference in New Issue
Block a user