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Checkpoint scheduling itinerary changes.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78564 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
David Goodwin
2009-08-10 15:56:13 +00:00
parent d94a4e5d8d
commit bcf81629b8
3 changed files with 53 additions and 28 deletions
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20
lib/Target/ARM/ARMSchedule.td
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@@ -10,11 +10,10 @@
//===----------------------------------------------------------------------===//
// Functional units across ARM processors
//
def FU_iALU : FuncUnit; // Integer alu unit
def FU_iLdSt : FuncUnit; // Integer load / store unit
def FU_FpALU : FuncUnit; // FP alu unit
def FU_FpLdSt : FuncUnit; // FP load / store unit
def FU_Br : FuncUnit; // Branch unit
def FU_Pipe0 : FuncUnit; // pipeline 0 issue
def FU_Pipe1 : FuncUnit; // pipeline 1 issue
def FU_LdSt0 : FuncUnit; // pipeline 0 load/store
def FU_LdSt1 : FuncUnit; // pipeline 1 load/store
//===----------------------------------------------------------------------===//
// Instruction Itinerary classes used for ARM
@@ -30,7 +29,16 @@ def IIC_Br : InstrItinClass;
//===----------------------------------------------------------------------===//
// Processor instruction itineraries.
def GenericItineraries : ProcessorItineraries<[]>;
def GenericItineraries : ProcessorItineraries<[
InstrItinData<IIC_iALU , [InstrStage<1, [FU_Pipe0]>]>,
InstrItinData<IIC_iLoad , [InstrStage<1, [FU_Pipe0]>, InstrStage<1, [FU_LdSt0]>]>,
InstrItinData<IIC_fpLoad , [InstrStage<1, [FU_Pipe0]>, InstrStage<1, [FU_LdSt0]>]>,
InstrItinData<IIC_iStore , [InstrStage<1, [FU_Pipe0]>]>,
InstrItinData<IIC_fpStore , [InstrStage<1, [FU_Pipe0]>]>,
InstrItinData<IIC_fpALU , [InstrStage<1, [FU_Pipe0]>]>,
InstrItinData<IIC_Br , [InstrStage<1, [FU_Pipe0]>]>
]>;
include "ARMScheduleV6.td"
include "ARMScheduleV7.td"