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[SystemZ] Extend test-under-mask support to high GR32s
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191773 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1386,6 +1386,11 @@ class BinaryRIPseudo<SDPatternOperator operator, RegisterOperand cls,
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let Constraints = "$R1 = $R1src";
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let Constraints = "$R1 = $R1src";
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}
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}
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// Like CompareRI, but expanded after RA depending on the choice of register.
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class CompareRIPseudo<SDPatternOperator operator, RegisterOperand cls,
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Immediate imm>
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: Pseudo<(outs), (ins cls:$R1, imm:$I2), [(operator cls:$R1, imm:$I2)]>;
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// Like StoreRXY, but expanded after RA depending on the choice of registers.
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// Like StoreRXY, but expanded after RA depending on the choice of registers.
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class StoreRXYPseudo<SDPatternOperator operator, RegisterOperand cls,
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class StoreRXYPseudo<SDPatternOperator operator, RegisterOperand cls,
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bits<5> bytes, AddressingMode mode = bdxaddr20only>
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bits<5> bytes, AddressingMode mode = bdxaddr20only>
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@ -910,6 +910,14 @@ SystemZInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
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expandRIPseudo(MI, SystemZ::XILF, SystemZ::XIHF, false);
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expandRIPseudo(MI, SystemZ::XILF, SystemZ::XIHF, false);
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return true;
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return true;
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case SystemZ::TMLMux:
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expandRIPseudo(MI, SystemZ::TMLL, SystemZ::TMHL, false);
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return true;
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case SystemZ::TMHMux:
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expandRIPseudo(MI, SystemZ::TMLH, SystemZ::TMHH, false);
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return true;
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case SystemZ::RISBMux: {
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case SystemZ::RISBMux: {
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bool DestIsHigh = isHighReg(MI->getOperand(0).getReg());
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bool DestIsHigh = isHighReg(MI->getOperand(0).getReg());
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bool SrcIsHigh = isHighReg(MI->getOperand(2).getReg());
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bool SrcIsHigh = isHighReg(MI->getOperand(2).getReg());
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@ -1140,16 +1140,22 @@ let mayLoad = 1, Defs = [CC], Uses = [R0L] in
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// Test under mask.
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// Test under mask.
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let Defs = [CC] in {
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let Defs = [CC] in {
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// TMxMux expands to TM[LH]x, depending on the choice of register.
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def TMLMux : CompareRIPseudo<z_tm_reg, GRX32, imm32ll16>,
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Requires<[FeatureHighWord]>;
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def TMHMux : CompareRIPseudo<z_tm_reg, GRX32, imm32lh16>,
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Requires<[FeatureHighWord]>;
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def TMLL : CompareRI<"tmll", 0xA71, z_tm_reg, GR32, imm32ll16>;
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def TMLL : CompareRI<"tmll", 0xA71, z_tm_reg, GR32, imm32ll16>;
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def TMLH : CompareRI<"tmlh", 0xA70, z_tm_reg, GR32, imm32lh16>;
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def TMLH : CompareRI<"tmlh", 0xA70, z_tm_reg, GR32, imm32lh16>;
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def TMHL : CompareRI<"tmhl", 0xA73, z_tm_reg, GRH32, imm32ll16>;
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def TMHL : CompareRI<"tmhl", 0xA73, z_tm_reg, GR64, imm64hl16>;
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def TMHH : CompareRI<"tmhh", 0xA72, z_tm_reg, GRH32, imm32lh16>;
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def TMHH : CompareRI<"tmhh", 0xA72, z_tm_reg, GR64, imm64hh16>;
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defm TM : CompareSIPair<"tm", 0x91, 0xEB51, z_tm_mem, anyextloadi8, imm32zx8>;
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defm TM : CompareSIPair<"tm", 0x91, 0xEB51, z_tm_mem, anyextloadi8, imm32zx8>;
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}
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}
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def : CompareGR64RI<TMLL, z_tm_reg, imm64ll16>;
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def : CompareGR64RI<TMLL, z_tm_reg, imm64ll16, subreg_l32>;
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def : CompareGR64RI<TMLH, z_tm_reg, imm64lh16>;
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def : CompareGR64RI<TMLH, z_tm_reg, imm64lh16, subreg_l32>;
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def : CompareGR64RI<TMHL, z_tm_reg, imm64hl16, subreg_h32>;
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def : CompareGR64RI<TMHH, z_tm_reg, imm64hh16, subreg_h32>;
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Prefetch
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// Prefetch
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@ -113,11 +113,11 @@ multiclass CondStores64<Instruction insn, Instruction insninv,
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}
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}
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// INSN performs a comparison between a 32-bit register and a constant.
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// INSN performs a comparison between a 32-bit register and a constant.
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// Record that it is equivalent to comparing the low word of a GR64 with IMM.
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// Record that it is equivalent to comparing subreg SUBREG of a GR64 with IMM.
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class CompareGR64RI<Instruction insn, SDPatternOperator compare,
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class CompareGR64RI<Instruction insn, SDPatternOperator compare,
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Immediate imm>
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Immediate imm, SubRegIndex subreg>
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: Pat<(compare GR64:$R1, imm:$I2),
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: Pat<(compare GR64:$R1, imm:$I2),
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(insn (EXTRACT_SUBREG GR64:$R1, subreg_l32),
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(insn (EXTRACT_SUBREG GR64:$R1, subreg),
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(imm.OperandTransform imm:$I2))>;
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(imm.OperandTransform imm:$I2))>;
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// Try to use MVC instruction INSN for a load of type LOAD followed by a store
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// Try to use MVC instruction INSN for a load of type LOAD followed by a store
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@ -525,3 +525,32 @@ define i32 @f24(i32 %old) {
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"=r,h,h,0"(i32 %res1, i32 %and3, i32 %and4)
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"=r,h,h,0"(i32 %res1, i32 %and3, i32 %and4)
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ret i32 %res2
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ret i32 %res2
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}
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}
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; Test TMxx involving mixtures of high and low registers.
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define i32 @f25(i32 %old) {
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; CHECK-LABEL: f25:
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; CHECK-DAG: tmll %r2, 1
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; CHECK-DAG: tmlh %r2, 1
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; CHECK: stepa [[REG1:%r[0-5]]],
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; CHECK-DAG: tmhl [[REG1]], 1
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; CHECK-DAG: tmhh [[REG1]], 1
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; CHECK: stepb %r2,
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; CHECK: br %r14
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%and1 = and i32 %old, 1
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%and2 = and i32 %old, 65536
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%cmp1 = icmp eq i32 %and1, 0
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%cmp2 = icmp eq i32 %and2, 0
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%sel1 = select i1 %cmp1, i32 100, i32 200
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%sel2 = select i1 %cmp2, i32 100, i32 200
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%res1 = call i32 asm "stepa $0, $1, $2",
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"=h,r,r"(i32 %sel1, i32 %sel2)
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%and3 = and i32 %res1, 1
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%and4 = and i32 %res1, 65536
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%cmp3 = icmp eq i32 %and3, 0
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%cmp4 = icmp eq i32 %and4, 0
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%sel3 = select i1 %cmp3, i32 100, i32 200
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%sel4 = select i1 %cmp4, i32 100, i32 200
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%res2 = call i32 asm "stepb $0, $1, $2",
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"=r,h,h"(i32 %sel3, i32 %sel4)
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ret i32 %res2
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}
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