From bd272999dd12bf0ac51048f546a3632998cede5b Mon Sep 17 00:00:00 2001
From: Misha Brukman <brukman+llvm@gmail.com>
Date: Wed, 2 Jul 2003 18:27:47 +0000
Subject: [PATCH] The classes F4_3 and F4_4 have an `rd' operand that needs to
 be set.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7073 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/Target/SparcV9/SparcV9_F4.td | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/lib/Target/SparcV9/SparcV9_F4.td b/lib/Target/SparcV9/SparcV9_F4.td
index 2a2e467c575..981c9f0f764 100644
--- a/lib/Target/SparcV9/SparcV9_F4.td
+++ b/lib/Target/SparcV9/SparcV9_F4.td
@@ -80,11 +80,13 @@ class F4_2<bits<2> opVal, bits<6> op3Val, string name> : F4_rs1simm11rd {
 class F4_3<bits<2> opVal, bits<6> op3Val, bits<4> condVal,
            string name> : F4_condcc {
   bits<5> rs2;
+  bits<5> rd;
 
   set op = opVal;
   set op3 = op3Val;
   set cond = condVal;
   set Name = name;
+  set Inst{29-25} = rd;
   set Inst{13} = 0; // i bit
   //set Inst{10-5} = dontcare;
   set Inst{4-0} = rs2;
@@ -99,6 +101,7 @@ class F4_4<bits<2> opVal, bits<6> op3Val, bits<4> condVal,
   set op3  = op3Val;
   set cond = condVal;
   set Name = name;
+  set Inst{29-25} = rd;
   set Inst{13} = 1; // i bit
   set Inst{10-0} = sim11;
 }