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https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-19 19:29:31 +00:00
Added support to STORE and shifts to DAG to DAG isel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24525 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -49,7 +49,7 @@ namespace {
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GlobalValue *GV;
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X86ISelAddressMode()
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: BaseType(RegBase), Scale(1), IndexReg(), Disp(), GV(0) {
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: BaseType(RegBase), Scale(1), IndexReg(), Disp(0), GV(0) {
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}
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};
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}
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@ -267,7 +267,7 @@ bool X86DAGToDAGISel::MatchAddress(SDOperand N, X86ISelAddressMode &AM) {
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SDOperand X86DAGToDAGISel::Select(SDOperand Op) {
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SDNode *N = Op.Val;
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MVT::ValueType OpVT = Op.getValueType();
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MVT::ValueType OpVT = N->getValueType(0);
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unsigned Opc;
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if (N->getOpcode() >= ISD::BUILTIN_OP_END)
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@ -275,9 +275,13 @@ SDOperand X86DAGToDAGISel::Select(SDOperand Op) {
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switch (N->getOpcode()) {
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default: break;
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case ISD::SHL:
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case ISD::SRL:
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case ISD::SRA:
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if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
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if (CN->getValue() == 1) { // X = SHL Y, 1 -> X = ADD Y, Y
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if (N->getOpcode() == ISD::SHL && CN->getValue() == 1) {
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// X = SHL Y, 1 -> X = ADD Y, Y
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switch (OpVT) {
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default: assert(0 && "Cannot shift this type!");
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case MVT::i8: Opc = X86::ADD8rr; break;
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@ -288,8 +292,38 @@ SDOperand X86DAGToDAGISel::Select(SDOperand Op) {
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CurDAG->SelectNodeTo(N, Opc, MVT::i32, Tmp0, Tmp0);
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return SDOperand(N, 0);
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}
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} else {
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static const unsigned SHLTab[] = {
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X86::SHL8rCL, X86::SHL16rCL, X86::SHL32rCL
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};
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static const unsigned SRLTab[] = {
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X86::SHR8rCL, X86::SHR16rCL, X86::SHR32rCL
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};
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static const unsigned SRATab[] = {
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X86::SAR8rCL, X86::SAR16rCL, X86::SAR32rCL
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};
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switch (OpVT) {
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default: assert(0 && "Cannot shift this type!");
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case MVT::i1:
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case MVT::i8: Opc = 0; break;
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case MVT::i16: Opc = 1; break;
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case MVT::i32: Opc = 2; break;
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}
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switch (N->getOpcode()) {
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default: assert(0 && "Unreachable!");
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case ISD::SHL: Opc = SHLTab[Opc]; break;
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case ISD::SRL: Opc = SRLTab[Opc]; break;
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case ISD::SRA: Opc = SRATab[Opc]; break;
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}
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SDOperand Tmp0 = Select(N->getOperand(0));
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CurDAG->SelectNodeTo(N, Opc, MVT::i32, Tmp0);
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return SDOperand(N, 0);
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}
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break;
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case ISD::RET: {
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SDOperand Chain = Select(N->getOperand(0)); // Token chain.
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switch (N->getNumOperands()) {
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@ -326,7 +360,7 @@ SDOperand X86DAGToDAGISel::Select(SDOperand Op) {
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}
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case ISD::LOAD: {
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switch (N->getValueType(0)) {
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switch (OpVT) {
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default: assert(0 && "Cannot load this type!");
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case MVT::i1:
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case MVT::i8: Opc = X86::MOV8rm; break;
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@ -342,23 +376,69 @@ SDOperand X86DAGToDAGISel::Select(SDOperand Op) {
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// ???
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assert(0 && "Can't handle load from constant pool!");
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} else {
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SDOperand Chain = Select(N->getOperand(0)); // Token chain.
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X86ISelAddressMode AM;
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SDOperand Chain = Select(N->getOperand(0)); // Token chain.
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SelectAddress(N->getOperand(1), AM);
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SDOperand Scale = getI8Imm (AM.Scale);
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SDOperand Disp = AM.GV ? CurDAG->getTargetGlobalAddress(AM.GV, MVT::i32)
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SDOperand Disp = AM.GV
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? CurDAG->getTargetGlobalAddress(AM.GV, MVT::i32, AM.Disp)
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: getI32Imm(AM.Disp);
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if (AM.BaseType == X86ISelAddressMode::RegBase) {
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CurDAG->SelectNodeTo(N, Opc, N->getValueType(0), MVT::Other,
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CurDAG->SelectNodeTo(N, Opc, OpVT, MVT::Other,
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AM.Base.Reg, Scale, AM.IndexReg, Disp, Chain);
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} else {
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SDOperand Base = CurDAG->getFrameIndex(AM.Base.FrameIndex, MVT::i32);
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CurDAG->SelectNodeTo(N, Opc, N->getValueType(0), MVT::Other,
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CurDAG->SelectNodeTo(N, Opc, OpVT, MVT::Other,
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Base, Scale, AM.IndexReg, Disp, Chain);
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}
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}
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return SDOperand(N, Op.ResNo);
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}
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case ISD::STORE: {
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SDOperand Chain = Select(N->getOperand(0)); // Token chain.
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SDOperand Tmp1 = Select(N->getOperand(1));
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X86ISelAddressMode AM;
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SelectAddress(N->getOperand(2), AM);
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Opc = 0;
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if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
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switch (CN->getValueType(0)) {
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default: assert(0 && "Invalid type for operation!");
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case MVT::i1:
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case MVT::i8: Opc = X86::MOV8mi; break;
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case MVT::i16: Opc = X86::MOV16mi; break;
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case MVT::i32: Opc = X86::MOV32mi; break;
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}
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}
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if (!Opc) {
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switch (N->getOperand(1).getValueType()) {
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default: assert(0 && "Cannot store this type!");
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case MVT::i1:
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case MVT::i8: Opc = X86::MOV8mr; break;
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case MVT::i16: Opc = X86::MOV16mr; break;
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case MVT::i32: Opc = X86::MOV32mr; break;
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case MVT::f32: Opc = X86::MOVSSmr; break;
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case MVT::f64: Opc = X86::FST64m; break;
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}
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}
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SDOperand Scale = getI8Imm (AM.Scale);
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SDOperand Disp = AM.GV
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? CurDAG->getTargetGlobalAddress(AM.GV, MVT::i32, AM.Disp)
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: getI32Imm(AM.Disp);
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if (AM.BaseType == X86ISelAddressMode::RegBase) {
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CurDAG->SelectNodeTo(N, Opc, MVT::Other,
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AM.Base.Reg, Scale, AM.IndexReg, Disp, Tmp1,
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Chain);
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} else {
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SDOperand Base = CurDAG->getFrameIndex(AM.Base.FrameIndex, MVT::i32);
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CurDAG->SelectNodeTo(N, Opc, MVT::Other,
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Base, Scale, AM.IndexReg, Disp, Tmp1, Chain);
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}
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}
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}
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return SelectCode(Op);
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